From 8704e53665910ba71e5bc3f99b32ead0060e1a3e Mon Sep 17 00:00:00 2001 From: Matthias Welwarsky Date: Fri, 16 Oct 2015 09:25:25 +0200 Subject: armv7a: fix handling of inner caches ARMv7 architecture allows up to 7 cache levels that are architecturally visible, as opposed to "system caches", which are outside of the domain defined by ARMv7 and require separate management. This patch enables detection and identification of caches at all levels. It also implements a new "flush-all" function that cleans & invalidates all cache levels to the "Point of Coherence". Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3024 Reviewed-by: Paul Fertser Tested-by: jenkins --- src/target/armv7a_cache_l2x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/target/armv7a_cache_l2x.c') diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c index 5af589e4..8b35fd89 100644 --- a/src/target/armv7a_cache_l2x.c +++ b/src/target/armv7a_cache_l2x.c @@ -179,7 +179,7 @@ static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx, struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) (armv7a_cache->outer_cache); - if (armv7a_cache->ctype == -1) { + if (armv7a_cache->info == -1) { command_print(cmd_ctx, "cache not yet identified"); return ERROR_OK; } -- cgit v1.2.3-18-g5258