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2019-11-07jtag: jtag_vpi: Add missing 'default' to switch statementAlexandru Gagniuc
If a new JTAG command is added, then GCC will complain that enumeration value not handled in switch. Make this consistent with other drivers, and add a 'default' case. Change-Id: I66d6d0db3fcae93ea246f2d4882ffff5dec14693 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://openocd.zylin.com/5340 Tested-by: jenkins Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-10-19libjaylink: Update to latest Git versionMarc Schink
This version adds two new USB PIDs and fixes a build issue under MSYS2. Change-Id: I753fab827783ea64e55e59d833742c9f70a28a2b Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5309 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-10-18nrf5: update links to compatibility matrixes for nrf5x variantsMirko Vogt
Change-Id: If51aa992ccbb8c9a2e502b74827a36a62010546d Signed-off-by: Mirko Vogt <mirko.vogt@sensorberg.com> Reviewed-on: http://openocd.zylin.com/4843 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-10-18target/cortex_a: Extract code to read/write from/to register to/from DCCFlorian Fainelli
In preparation for supporting the ARM MCRR and MRRC commands which will require using two 32-bit registers to read/write a 64-bit internal register, extract the common logic to read/write from/to a register to/from DCC and make that parameterized such that we can do this through not just r0. Change-Id: Iadb73f5cde8cf5961b5a18ddd198bf39d791e610 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-on: http://openocd.zylin.com/5227 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-10-18drivers/gw16012: remove useless cast on gw16012_portAntonio Borneo
The variable gw16012_port is of type uint16_t. There is no need for a cast to print it. Change the format modifier to PRIx16 Change-Id: I16fe688b9d235bae46525635d07849a00fba9548 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5195 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-10-18gdb_server: Support vRun packet, allow setting cmdline from GDBAndreas Fritiofson
GDB uses the vRun packet if available to restart a running process in extended remote mode. Support this like the R packet and set the semihosting command-line to allow it to be specified from GDB. Change-Id: I9cb812b22170630f782113c9927e46e0cd5b1f0f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/5186 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-10-18gdb-server: Create arch-specific structure type for every featureAlexey Brodkin
As it is mentioned here [1] type's ID is unique name within containing feature. That said if regs of the same type located in different features it's required to insert type definition at least in each feature. See more details in discussion here [2]. [1] https://sourceware.org/gdb/onlinedocs/gdb/Target-Description-Format.html#Types [2] https://github.com/foss-for-synopsys-dwc-arc-processors/openocd/commit/2a5f5125ac8fa0e1359b6be03b209f9f5d1ade82#r33460077 Change-Id: Id92b061cfbf47d5c032a02c2c406b28affd0b02a Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5179 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-10-18target/cortex_a: use aligned accesses for read/write cpu memory slowAntonio Borneo
Armv7a is able to read and write memory at un-aligned address, but only when bit SCTLR.A (Alignment check enable) is zero and the address belongs to a memory space with attribute "Normal" (see [1] chapter A3.2.1 "Unaligned data access"). In all the other cases the memory access will trigger an alignment fault data abort exception. Memory attributes are explained in [1] chapter A3.5 "Memory types and attributes and the memory order model". Disabling the MMU cause a change in memory attribute, as explained in [1] chapter B3.2 "The effects of disabling MMUs on VMSA behavior". This can cause several issues. e.g. a SW breakpoint on un-aligned 4-byte Thumb instruction, set when MMU is on, can be impossible to remove when MMU turns off. While is possible to check all the possible conditions before an un-aligned memory access, it's clearly more maintainable to skip such complexity and only perform aligned accesses. Check the alignment and eventually modify the data size before calling the functions cortex_a_{read,write}_cpu_memory_slow(). Change the comment in the two functions above to comply with the new behaviour. [1] ARM DDI 0406C.d - "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition" Change-Id: I57b4c11e7fa7e78aaaaee4406a5734b48db740ae Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5138 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-10-18adi_v5_jtag: avoid RAM exhaustion by limiting jtag queue sizeBohdan Tymkiv
Issue has been found when I tried to read 64 MiB QSPI flash bank. Bank is memory mapped, default_flash_read() is used for 'flash read_bank' command. OpenOCD consumed as much as 6.8 GiB of RAM during this process. Investigation showed that this happens because JTAG queue is not limited in any way. OpenOCD queues 16 millions of AP reads allocating all corresponding data structures. Most of this memory is allocated in: cmd_queue_alloc (commands.c) - 4.2 GiB dap_cmd_new (adi_v5_jtag.c) - 2.25GiB This patch implements a pool of "struct dap_cmd" objects using linked list. Objects are taken from a pool in "dap_cmd_new()" and returned to the pool when they are not needed. Size of the pool is limited to 64K of objects, JTAG queue is forcibly executed when this limit is reached. Checked with Valgrind and Clang analyzer - no new warnings. Change-Id: I5aaaecce5ed71414f7965a2598f49742f6a6b2b5 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4948 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-10-18nrf5: Fix misuse of flash bank numberAndreas Fritiofson
Make driver_priv point directly into the corresponding chip bank structure and add a pointer to it to get back to its chip when it's needed. This removes the need to keep track of any bank number, either global or chip- local. In addition, it simplifies the cases where the chip structure was just used to access the chip bank fields; now they are directly accessible. Change-Id: Iaa353cd4fa7d8ff94c2ef69028c7cb32fade0420 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/4775 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-10-18target: Switch to target_read_buffer() in verify_image fallbackAndreas Fritiofson
The current code checks the count to determine whether to read bytes or words. However it fails to consider whether the base address is suitably aligned. Instead use the target_read_buffer() function which is for exactly this purpose and generates optimal accesses with natural alignment. Change-Id: I32ab5417890ee2219902df1529bc220fe353b4c7 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3217 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-10-15src/flash/startup.tcl: Add preverify to program commandMoritz 'Morty' Strübe
The preverify option allows to check whether flashing is necessary. If the target is flashed often/automatically this can save time and preserve the flash. This is expecially helpful in CI environments. Change-Id: Iead0a269e1a772b751d4dd9e8b53b2fecc874624 Signed-off-by: Moritz 'Morty' Strübe <moritz.struebe@redheads.de> Reviewed-on: http://openocd.zylin.com/5292 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2019-10-15Add complete JTAG debug logging.Tim Newsome
Sample output, with default_interface_jtag_execute_queue replaced by dijeq to satisfy commit message line length check: Debug: 646 18 core.c:847 dijeq(): JTAG IR SCAN to RUN/IDLE Debug: 647 18 core.c:852 dijeq(): 5b out: 11 Debug: 648 18 core.c:847 dijeq(): JTAG DR SCAN to RUN/IDLE Debug: 649 18 core.c:852 dijeq(): 40b out: 4400000001 Debug: 650 18 core.c:857 dijeq(): 40b in: 4400000000 Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: I014e9e3a77755413b36edfcede2ab8f6aa08061b Reviewed-on: http://openocd.zylin.com/4451 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-10-15Add wall clock timeout warning to mpsse_flush()Tim Newsome
I think that libusb_handle_events_timeout_completed is supposed to make progress or time out, but sometimes we hit a case where it makes no progress, and mpsse_flush() loops forever. This wall clock timeout notifies the user that this is going on. When I wrote this code, this bug would reproduce every hour or two, but right now it's not happening for me. Change-Id: I7eb66f43462298e263a48048aa0c8769095661eb Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4767 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-10-02efm32: use device-specific MSC base for EFM32TG11BChristian Meusel
According to the reference manual it should be 0x40000000. Flashing (and booting) a firmware with this MSC base was successful. Change-Id: I739e67d36555b8170a3b8e26f54cf1c09ce8424b Signed-off-by: Christian Meusel <christian.meusel@posteo.de> Reviewed-on: http://openocd.zylin.com/5263 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-24src/jtag/aice: Fix obviously incorrect bit op.Seth LaForge
Fix expression "(pin_status | 0x4)" which was always true rather than testing a bit. Untested - was clearly not expressing the intent of the author by inspection. Found by automated tooling and rtrieu@google.com. Signed-off-by: Seth LaForge <sethml@google.com> Change-Id: I4bb91e60e8ce9757bf21976cc48de6f85a39c68d Reviewed-on: http://openocd.zylin.com/5301 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-24helper/command: clear errno before calling parserChristopher Head
The C standard says that errno is set to ERANGE if an out-of-range value is returned by strtol, strtoul, et. al., but it does not say that errno is cleared if the function is successful (and, indeed, it is not on glibc). This means that, if errno is ERANGE before strtol is called, and if the value to be converted is exactly the maximum (or, for a signed conversion, the minimum) legal value, COMMAND_PARSE_NUMBER will erroneously indicate that the value is out of range. Change-Id: I8a8b50a815b408a38235968f1c1d70297ea1a6aa Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5298 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-24flash/nor/tcl: Fix usage of 'flash erase_sector' commandMarc Schink
Change-Id: I2141e377a0531cab8d1140049a2ee7721d30cfdc Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5299 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-18esirisc_flash: Rename PAGE_SIZE to FLASH_PAGE_SIZEKhem Raj
PAGE_SIZE is defined in system includes on some systems, this would avoid the unintended conflict Fixes | src/flash/nor/esirisc_flash.c:95:9: error: 'PAGE_SIZE' macro redefined [-Werror,-Wmacro-redefined] | #define PAGE_SIZE 4096 | ^ | /mnt/a/yoe/build/tmp/work/core2-64-yoe-linux-musl/openocd/0.10+gitrAUTOINC+7ee618692f-r0/recipe-sysroot/usr/inclu de/limits.h:89:9: note: previous definition is here | #define PAGE_SIZE PAGESIZE Change-Id: I195b303fc88a7c848ca4e55fd6ba893796df55cc Signed-off-by: Khem Raj <raj.khem@gmail.com> Reviewed-on: http://openocd.zylin.com/5180 Tested-by: jenkins Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-08flash/nor/stm32h7x: remove unused 'pages_per_sector' from stm32h7x_part_infoTarek BOCHKATI
Change-Id: I1b79c25cada574e3a9849f506443c836bd707604 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5289 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
2019-09-08flash/nor/stm32h7x: remove flash size information from device nameTarek BOCHKATI
There is no sense in displaying the max size (2M) as there is variants of this device with reduced flash size Change-Id: I40574064d75fdf2a038044c81038a6d7abc6c4dd Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5288 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-08flash/nor: flash driver for Synwit SWM050 MCUsCaleb Szalacinski
SWM050 is a series of MCU product by Foshan Synwit Tech, which is available in TSSOP-8 or SSOP-16 packages. Adds flash driver for the internal 8KiB flash of the MCU. The registers are based on reverse engineering the J-Flash blob provided by the vendor. Also adds a pre-made cfg file. Change-Id: I0b29f0c0d062883542ee743e0750a4c6b6609ebd Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Caleb Szalacinski <contact@skiboy.net> Reviewed-on: http://openocd.zylin.com/4927 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-08target/dsp563xx: dsp563xx restore reg supportHan Hartgers
Added "exist=true" field to the reg_list struct to make access to the dsp563xx registers again possible. Without it defaults to exist=false and all the reg related functions will return nothing. Fixes regression from b5964191f0d2fc3ace607af001df3d57cbfbaf2b Change-Id: I9c256346735b8d66919c4ba83f528a8afca46ff9 Signed-off-by: Han Hartgers <han.hartgers@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5239 Tested-by: jenkins
2019-09-08src/flash/nand: Fix some operator precedence bugs.Seth LaForge
Fix two expressions where precedence of operator | vs ?: was clearly confused. Untested - was clearly not expressing the intent of the author by inspection. Found by automated tooling and rtrieu@google.com. Change-Id: I46f190154797f8affc761caf3a15a1a9db53d702 Signed-off-by: Seth LaForge <sethml@google.com> Reviewed-on: http://openocd.zylin.com/5281 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-08-28gdb_server, rtos: Fine-grained RTOS register accessTim Newsome
1. Add get_thread_reg() to rtos. It's used in rtos_get_gdb_reg() to read the value of a single register, instead of reading all register values by calling get_thread_reg_list(). 2. Add set_reg() to rtos. gdb_server uses this to change a single register value for a specific thread. 3. Add target_get_gdb_reg_list_noread() so it's possible for gdb to get a list of registers without attempting to read their contents. The clang static checker doesn't find any new problems with this change. Change-Id: I77f792d1238cb015b91527ca8cb99593ccc8870e Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/5114 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-08-04flash/nor/core: fix some minor typoTarek BOCHKATI
Change-Id: I03832b3e4a6eaadfd87729a3a898e0a2cd30931a Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5264 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-07-28mflash: Remove this broken flash driverAndreas Fritiofson
This is causing repeated build failures. Its design is so fundamentally broken that if someone actually wants to use it, a full rewrite is the only option. So it's not even worth deprecating in the hope that someone will notice and fix it, just get rid of it. Change-Id: I513069919a3873bd69253110f7fb6f622ee7d061 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/5243 Tested-by: jenkins Reviewed-by: Jeffrey Booher-Kaeding <Jeff.Booher-Kaeding@arm.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-06-20cortex_m: set C_DEBUGEN in soft_reset_haltAntonio Borneo
The command "soft_reset_halt" is deprecated since mid 2013 with the commit 146dfe32956d ("cortex_m: deprecate soft_reset_halt"). Nevertheless it is still extremely useful with multicore chips where it allows to reset only one of the cores, option not available through asserting the chip-wide srst. Without a better replacement of the command, it's worth fixing it. Accordingly to ARM DDI 0403E.d, chapter C1.4.1 "Entering Debug state on leaving reset state", to halt the core at reset both bits DHCSR.C_DEBUGEN and DEMCR.VC_CORERESET must be set. Current code only sets the latter bit, relying on having C_DEBUGEN already set through other commands, e.g. "halt". This prevents the command "soft_reset_halt" to work if issued as very first command. Set the bit C_DEBUGEN in command "soft_reset_halt". Change-Id: I66bfd6a0da1fca5049dea037b4d258cf6f842966 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4987 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-20helper/options: simplify the code using command_run_linef()Antonio Borneo
Thanks to command_run_linef() there is no need to pre-build the command using alloc_printf(). Change-Id: Iccfebd6063d1ac162f090fe2309b1f51bebf0214 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5226 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-20helper/command: make command_run_line reentrantChristopher Head
The `command_run_line` function contains a comment saying it should be reentrant. However, it isn’t: it NULLs out `current_target_override` and doesn’t restore it before returning, and it changes the `context` associated data of the `interp` object and then deletes that associated data before returning rather than restoring it to its previous value. Change-Id: I84fd46ef7173f08cf7c57b9a5b76e4986a60816f Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5223 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-19target/cortex_m: Add support for AHB5-APMarc Schink
The AHB5-AP is implemented in Cortex-M23/33 based devices. Change-Id: I505954a2e2c6462ce0aa96eba1d55b016c5028b9 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5232 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2019-06-19target/arm_adiv5: Add type for AHB5-APMarc Schink
This access port type comes with the AMBA 5 protocol specification, see 'C1.3 AP' in ARM IHI 0031D. Change-Id: I3c4f0a69230daaf4f5f979de6213fe3c025a089a Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5231 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
2019-06-19Support for debugging on ARMv8-M CPUsOmair Javaid
This patch adds ARMv8-M CPUs detection logic in ARMv7m target specific code. Also adds a slightly different watchpoint manipulation logic for ARMv8-M. This is based on ARMv8-M architecture reference manual. Tested on ARM Musca A board. Change-Id: I0652560954ef02c378a7067fab586edf39d3e9cc Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4997 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-14target/cortex_a: remove dependency from jtag queueAntonio Borneo
Replace jtag specific API jtag_add_reset() with transport independent API adapter_{de}assert_reset(). Change-Id: I1b917a4c1205115c4e0315373d81a9305e931258 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4944 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-14target/aarch64: remove dependency from jtag queueAntonio Borneo
Replace jtag specific API jtag_add_reset() with transport independent API adapter_{de}assert_reset(). Change-Id: I32c43e2e47366363521fa3f387de9e2fb1c20852 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4943 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-13jtag: fix error on TCL command "return" in jtag event handlerAntonio Borneo
The TCL command "return" always returns error code JIM_RETURN, to indicate that the effective error code and message are elsewhere. In the current implementation, the caller of jtag's event only checks for return code JIM_OK and considers any other value, including JIM_RETURN, as an error condition. It can be tested running openocd on a jtag target and adding a jtag event "setup" with a single line "return", e.g. openocd -f board/ti_cc3200_launchxl.cfg \ -c 'jtag configure cc32xx.cpu -event setup return' to get the message: ../src/jtag/core.c:1599: Error: in procedure 'jtag_init' called at file "../src/jtag/core.c", line 1599 Modify jtag_tap_handle_event() to detect the specific return value of the "return" command and to test the real error code that is, eventually, specified to the TCL "return" command. Change-Id: I6d6febc15ef169638afffbffc1810e0b84fcf5c8 Reported-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5199 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-13target: fix error on TCL command "return" in target event handlerAntonio Borneo
The TCL command "return" always returns error code JIM_RETURN, to indicate that the effective error code and message are elsewhere. In the current implementation, the caller of target's event only checks for return code JIM_OK and considers any other value, including JIM_RETURN, as an error condition, thus dumping the call-trace. The execution is not stopped because the error is not further propagated, but the error message is annoying and misleading. It can be tested running openocd -f ./test.cfg using the following script "test.cfg". You can replace the board file in line 1, to use a board available in your lab: 1 source [find board/st_nucleo_f4.cfg] 2 [target current] configure -event reset-start {} 3 [target current] configure -event reset-end {return} 4 init 5 proc a {} {[target current] invoke-event reset-start} 6 proc b {} {[target current] invoke-event reset-end} 7 proc c {} {a;b;echo "arrived at the end"} 8 c 9 shutdown The execution produces: ./test.cfg:7: Error: in procedure 'c' called at file "./test.cfg", line 8 in procedure 'b' called at file "./test.cfg", line 7 arrived at the end that shows the call-trace but does not halt the execution. The developer can avoid using the "return" command in the event body by defining a TCL procedure that implements the handler and that contains the "return" command, reducing the handler body to a simple call to the procedure above. But this approach is either not documented nor always intuitive while writing the handler, causing waste of time to look for the false error. Modify target_handle_event() to detect the specific return value of the "return" command and to test the real error code that is, eventually, specified to the TCL "return" command. Change-Id: I2b860bab7233c6ed13ee4098e348d7533e1c4626 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4974 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-13flash/stm32h7x: fix register names to comply with RM0399 Rev2 and RM0433 Rev6Tarek BOCHKATI
Change-Id: I085d86a2a47f4aeef93a99238e3b80ee294d46df Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5192 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-13jtag: drivers: buspirate: chunk SWD switch sequence transfer.Tilman Sauerbeck
Commit c2e18bfaeafd changed the size of the JTAG-to-SWD sequence from 15 bytes to 17 bytes. This broke SWD switch sequence transfer for buspirate, since buspirate packets can only hold a payload of up to 16 bytes and we tried to fit the whole sequence in a single packet. Splitting up the sequence transfer in appropriately sized packets makes buspirate SWD work again (successfully tested with buspirate firmwares v6.1 and v7.0). Change-Id: Ib5b412b9e77287d705d2762e31c16d30318b50e3 Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de> Reviewed-on: http://openocd.zylin.com/5200 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-13jtag/drivers/jtag_usb_common: fix typoChristopher Head
Change-Id: If1f56fd5d610b993a4ecbc900fac9f90638037c9 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5202 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-12target: make target re-configuration possible againTomas Vanek
Before commit 877cec20dca6e78f9f029f0f173879cda101a6c2 ("command: check command mode for native jim commands") all the jim commands were erroneously treated as they had mode COMMAND_ANY. The command '$_TARGET configure -xxx' was therefore applicable on running OpenOCD to change the target configuration. It is handy e.g. for changing an event handler or changes of the work area. Change 'configure' command .mode to COMMAND_ANY to make it possible again. The only parameter which cannot be re-configured after init is -gdb-port. Test the command mode and refuse setting of gdb port after init. Change-Id: I88493ac10a46647dc52a88fbc9f8ce6b5ba3bcd0 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5214 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-12fix XScale register accessMichael Schwingen
since b5964191f0, all XScale-specific registers were missing, breaking config scripts. Change-Id: Ia56f3ca17500ba54bd08f417e9a5aaaa8a1be8c4 Signed-off-by: Michael Schwingen <spam-openocd@discworld.dascon.de> Reviewed-on: http://openocd.zylin.com/5136 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-12mem_ap: fix format of logged addressesAntonio Borneo
The macro TARGET_ADDR_FMT, defined in helper/types.h, already includes the prefix "0x" in front of the hexadecimal number, being defined as: #define TARGET_ADDR_FMT "0x%8.8" TARGET_PRIxADDR An additional "0x" is present in mem_ap; it prints debug messages with a double "0x" before the address: Debug: 2921 34180 mem_ap.c:153 mem_ap_write_memory(): Writing memory at physical address 0x0x5000000c; size 4; count 1 Remove the incorrect hexadecimal prefix. Change-Id: I38f19ed2a2f542bd5df53e947a2604f1cbe80e08 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5222 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-12ARMv8: Update rtos_reg storage from 8 to 16 bytesDaniel Goehring
To support 128 bit registers, the rtos_reg structure value array needs to be updated from 8 to 16 bytes. Tested by reading ARMv8 NEON FP regs on an Ampere eMAG 8180 with GDB. Change-Id: I7f3fe1a5b2def599d021787fbe9cdd51f92859a4 Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Reviewed-on: http://openocd.zylin.com/5209 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-12armv7a_mmu: Add support for decoding Super SectionsFlorian Fainelli
The ARMv7-A architecture supports super sections which allows mapping physical addresses up to 40-bit into a 32-bit virtual address using the short descriptor format (see ARM DDI 0406C.c section B4.1.112 for details). Change-Id: I8e64d0e93e36ae7a7da7b7bf2a8342856bb044f1 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-on: http://openocd.zylin.com/5212 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-12armv7a_mmu: Do not restrict virtual addresses to uint32_tFlorian Fainelli
In preparation for adding super section decoding, do not restrict armv7a_mmu_translate_va_pa() to 32-bit virtual addresses since ARMv7-A processors with VMSA extensions (including LPAE) can issue wider physical addresses. Update casting to uint32_t where necessary. Change-Id: Id1c3d0d5ac324cbdc334259d9ea75fe4981671a1 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-on: http://openocd.zylin.com/5211 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-12armv7a_mmu: Remove armv7a_mmu_translate_va()Florian Fainelli
This function is not used anywhere in the tree, remove it, such that we only have a single function moving forward that might need to deal with short vs. long format specifics. Change-Id: I80e81cd7eba1e028d1afaeaedb675b46c0ca6fa1 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-on: http://openocd.zylin.com/5213 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-12armv7a_mmu: Check earlier for PAR readFlorian Fainelli
Check earlier that the read of the PAR register was successful instead of starting the decoding and then checking for an error reading that register. Change-Id: Id96c2b2f76d2d1c745fcfa55ad4c1e6db92106f9 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-on: http://openocd.zylin.com/5215 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-10target/armv7m: fix register number in armv7m_get_core_reg()Tomas Vanek
armv7m_get_core_reg() calls arm->read_core_reg() arm->read_core_reg() expects the register number as an index to core reglist, not an ARMv7M specific register code. Use reg->number instead of armv7m_reg->num. The change solves assert src/target/armv7m.c:222: armv7m_read_core_reg: Assertion `num < (int)armv7m->arm.core_cache->num_regs' failed. when gdb 'info reg' is issued on a Cortex-M target and no cortex_m_debug_entry() has been called since OpenOCD start (target was halted before OpenOCD start). Change-Id: I32a2294693ef979b613be93aeceb3b0eb06ee6df Ticket: https://sourceforge.net/p/openocd/tickets/216/ Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5203 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-06-06jtag: set default "jtag_only" to uninitialized transportsAntonio Borneo
For legacy support, drivers that do not define a list of transports get identified as jtag_only. Cleanup this old crust and initialize properly the transports field in the jtag_interface for all the drivers. Change-Id: I9c86064e5d05bd0212bc18f4424414e615e617fe Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4893 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
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