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2017-09-15Some hack for MIPS, don't remember the detailsmips-hackDavid Barksdale
2015-12-01cortex_a: fix fast-mode memory readsMatthias Welwarsky
cortex_a_read_apb_ab_memory_fast() uses the wrong order of ITR and DSCR writes when setting up the transfer. ARM DDI0406C says in C8.2 regarding "Fast mode" operation to first switch to fast mode and then latch the instruction in ITR. Current implementation first wrote ITR, causing the instruction to be executed immediately, then switched to fast mode without an instruction latched. Repeated reading of DTRTX didn't execute LDC and thus replicated its current content into the whole buffer. This patch uses the following, revised algorithm: 1) switch to non-blocking mode and issue the LDC for the first word 2) if more than one word is to be read: - switch to fast mode - latch the LDC instruction into ITR (it is _not_ executed) - issue (count-1) reads of DTRTX register, each read returns the current content of DTRTX and re-issues the latched instruction -> now the second-to-last word is in the buffer and the LDC for the last word has been issued. 3) wait for the last instruction to complete 4) switch back to non-blocking mode 5) Read DTRTX for the last (or: only) word and put it into the buffer Change-Id: I44f5c585962ffa5af257c3d5a2a802c122b6b1e4 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3122 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30xsvf: output a warning suggesting using SVFPaul Fertser
Change-Id: Iff13019aa96c528268a2be029b4acd65a00a598e Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2907 Tested-by: jenkins
2015-11-30cortex_a: replace cortex_a_check_address functionMatthias Welwarsky
When accessing memory through the ARM core, privilege levels and mmu access permissions observed. Thus it depends on the current mode of the ARM core whether an access is possible or not. the ARM in USR mode can not access memory mapped to a higher privilege level. This means, if the ARM core is halted while executing at PL0, the debugger would be prevented from setting a breakpoint at an address with a higher privilege level, e.g. in the OS kernel. This is not desirable. cortex_a_check_address() tried to work around this by predicting if an access would fail and switched the ARM core to SVC mode. However, the prediction was based on hardcoded address ranges and only worked for Linux and a 3G/1G user/kernel space split. This patch changes the policy to always switch to SVC mode for memory accesses. It introduces two functions cortex_a_prep_memaccess() and cortex_a_post_memaccess() which bracket memory reads and writes. These function encapsulate all actions necessary for preparation and cleanup. Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3119 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: rework mmu manipulationMatthias Welwarsky
when disabling the mmu to access physical addresses, normally the d-cache must be disabled as well. Disabling the d-cache also requires a full clean&invalidate. However, since all memory writes are treated as write- through no-allocate and memory reads do not allocate cache lines, effectively the d-cache state does not change at all. We can therefore save the the d-cache disabling and flushing. This patch also simplifies the function a bit. Change-Id: Ia17c56a28f432156429cd4596107e3652b788e63 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3114 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: force cache and tlb bypass when cpu is in debug stateMatthias Welwarsky
for minimal impact on the hardware state, force all memory accesses to bypass the caches and tlbs. This may actually be the default, but ARM recommends in DDI0406C to set proper default values on debug init. Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3079 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: fix-up dcache clean and flush functions inner loop patternMatthias Welwarsky
Other cache functions use an updated pattern for the address range loop. Bring dcache clean and flush functions in line. Change-Id: Iccb4a05c49054471033a3403363110cb08245d5b Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3035 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: Update instruction cache after setting a soft breakpointMatthias Welwarsky
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint, to make sure the d-cache is clean and invalid at the breakpoint location down to PoC. Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint again, so that d-cache will pick up the modified code. Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint to memory to make the change visible to the CPU. Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3033 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: correctly handle invalidation of inner data cachesMatthias Welwarsky
D-Cache invalidate is a dangerous operation. It will only work correctly if full cache lines are invalidated. When partial cache lines are invalidated, i.e. the target address range does not start and end at a cache line boundary, cpu data writes outside of the target range will be dropped. This patch adds special treatment for partial cache lines by doing a clean & invalidate on the partial lines before invalidating the rest of the range. Change-Id: I64099ddb058638e990a7eb0ee911b9cc8f6f8901 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3034 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30armv7a: fix debug messages regarding cache on/off stateMatthias Welwarsky
Cache bits are not level specific, remove "l1" from debug message. Also, fix data/instruction mixup in armv7a_l1_i_cache_sanity_check() Change-Id: I259665ffe62c7ada5b4f98d3fd907e93662d4091 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3028 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: rework automatic flush-on-write handlingMatthias Welwarsky
The following changes are implemented: - Clean&Invalidate the VA range to PoC *before* the write takes place - Remove SMP handling since DCCIMVA instruction already maintains SMP coherence. - Remove separate Invalidate step Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3027 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: add d-cache virtual address range flush functionMatthias Welwarsky
This patch adds a function for cleaning & invalidating a virtual address range from the architecture caches down to the point of coherence. Change-Id: I4061ab023a3797fabc967f3a34498034841d52c6 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3026 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: remove indirection for cache info handlerMatthias Welwarsky
There's only one function left that handles cache info display, no need any more for a function pointer and runtime initialization. Change-Id: I90b09577f81607917b11f0ab5600a0e2dce223e2 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3025 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: fix handling of inner cachesMatthias Welwarsky
ARMv7 architecture allows up to 7 cache levels that are architecturally visible, as opposed to "system caches", which are outside of the domain defined by ARMv7 and require separate management. This patch enables detection and identification of caches at all levels. It also implements a new "flush-all" function that cleans & invalidates all cache levels to the "Point of Coherence". Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3024 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: remove special l2x flush-all and cache-info handlersMatthias Welwarsky
This patch is on the path to unified handlers for both inner and outer caches. It removes the special overrides installed when an outer cache is configured. Change-Id: I747f2762c6c8c76c700341cbf6cf500ff2a51476 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3022 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30armv7a: rename l2_cache to outer_cacheMatthias Welwarsky
The outer cache is not necessarily at L2 in a system. Rename functions to make that clear. Change-Id: Ia636a4844f50634f2bdf5cdce285febc1a47c11f Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3020 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30armv7a: remove l1 flush all data handlerOleksij Rempel
deprecated by new code. Change-Id: Ie3db627803a6aae38a5287bd3a748a78ab084b7d Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2801 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30add armv7a_cache handlersOleksij Rempel
This patch introduces, new command set and handlers for l1 and l2x caches. Patch set 10 folded the following changes into this one: Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415 If8d87a03281d0f4ad402909998e7834eb4837e79 I0749f129fa74e04f4e9c20d143a744f09ef750d8 Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/2800 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: add cortex_a_[read|write]_memory_ahbOleksij Rempel
Change-Id: I39c457274e1714a8d42233f7fc490fb58f5cb38e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2798 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: add cortex_a_[read|write]_bufferOleksij Rempel
Change-Id: I82011822d913aa7228f5c6262b540156494bedfe Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2797 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: remove cache handlers from cortex_a_write_phys_memoryOleksij Rempel
This was needed for ahb access Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2796 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: remove ahb support for phys_memory accessOleksij Rempel
Change-Id: I5b7c21c16e95cc1a3160e356d6e64f1f8c449e6e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2795 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-27adi_v5: Fix wrong ap valueAlamy Liu
Problem dap->ap_current is register value, not field value. it restores invalid ap when it calls dap_ap_select(dap, ap_old) later. * assume the current ap is 1, dap->ap_current value would be (1 << 24). ap_old = dap->ap_current; <-- ap_old = 1<<24 = 0x1000000. ... dap_ap_select(dap, ap_old); <-- select 0x1000000, not 1. * All AP registers accessing fail afterwards. One of the reproducible case(s): CORE residents in AP >= 1 dap_lookup_cs_component() being used to find PE(*). In most cases, PE would be found in AP==0, hence the problem is hidden. When AP number is 1, dap->ap_current would have the value of 1<<24. Anyone get the AP value with dap->ap_current and resotre it later would select the wrong AP and all accessing later would fail. The ARM Versatile and/or FPGA would have better chance to provide this kind of environment that PE residents in AP>=1. As they have an 'umbrella' system at AP0, and main system at AP>=1. * PE: Processing Element. AKA Core. See ARM Glossary at http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014g/ABCDEFGH.html Fix Use dap_ap_get_select() to get ap value. a. Retrieve current ap value by calling dap_ap_get_select(); src/flash/nor/kinetis.c src/target/arm_adi_v5.c b. The code is correct (dap->ap_current >> 24), but it's better to use dap_ap_get_select() so everything could be synchronized. src/flash/nor/sim3x.c Change-Id: I97b5a13a3fc5506cf287e299c6c35699374de74f Signed-off-by: Alamy Liu <alamy.liu@gmail.com> Reviewed-on: http://openocd.zylin.com/2935 Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-11-26jlink: Retrieve maximum speed from device.Marc Schink
If supported, the maximum transport speed is now retrieved from the device. Change-Id: I614f405ec91cf199c851781785fd26cbd10c37a6 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2955 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-26Improve J-Link driver and introduce libjaylink.Marc Schink
This patch uses libjaylink which is a library to access J-Link devices. As other tools which are not in the scope of OpenOCD also need to access J-Link devices a library is used. A firmware upgrade tool and an advanced configuration tool for J-Link devices are under development. Further versions of libjaylink will support additional features OpenOCD could benefit from. This includes TCP/IP as additional possibility to connect to J-Link devices as well as power tracing and device internal communication. The latter is used to access peripherals on some development boards (e.g EFM32 STK and DVK). Integration of libjaylink is realized with a git submodule like jimtcl. As libjaylink depends on libusb-1.0 only, no additional dependency is introduced for OpenOCD. All low-level JTAG and SWD implementations of the current driver are left untouched and therefore no incompabilities are to be expected. Improvements of this patch: * Support for more USB Product IDs, including those with the new scheme (0x10xx). The corresponding udev rules are also updated. * Device selection with serial number and USB address. * Adaptive clocking is now correctly implemented and only usable for devices with the corresponding capability. * The target power supply can now be switched without the need for changing configuration and power cycling the device. * Device configuration is more restrictive and only allowed if the required capabilities are available. * Device configuration now shows the changes between the current configuration of the device and the values that will be applied. * Device configuration is verified after it is written to the device exactly as the vendor software does. * Connection registration is now handled properly and checks if the maximum number of connections on a device is reached. This is also necessary for devices which are attached via USB to OpenOCD as some device models also support connections on TCP/IP. * Serial Wire Output (SWO) can now be captured. This feature is not documented by SEGGER however it is completely supported by libjaylink. This patch and libjaylink were tested on Ubuntu 14.04 (i386), Debian 7 (amd64), FreeBSD 10.0 (amd64) and Windows XP SP3 (32-bit) with the following device and target configurations: * JTAG: J-Link v8.0, v9.0 and v9.3 with AT91SAM7S256 * SWD: SiLabs EFM32 STK 3700 (EFM32GG990F1024) * SWD: J-Link v8.0, v9.0 and v9.3 with EFM32GG990F1024 * SWD: XMC 2Go (XMC1100) * SWD: XMC1100 Boot Kit (XMC1100) * SWD: IAR Systems / Olimex Eval Board (LPC1343F) * SWD: Nordic Semiconductor nRF51 Dongle (nRF51422) * SWD: SiLabs EZR32 WSTK 6220A (EZR32WG330FG60G) Except for Windows XP all builds are tested with Clang in addition to GCC. This patch and libjaylink are not tested on OSX yet. Change-Id: I8476c57d37c6091c4b892b183da682c548ca1786 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2598 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-26flash/nor/lpc2000: add alternative part ID for LPC1343Jakub Kubiak
http://support.code-red-tech.com/CodeRedWiki/DebugAccessChip > Note that once you have recovered debug access to your MCU, then in most cases you should then modify your Debug Configuration to turn vector catch off again. If this is not done, then this can cause problems in some circumstances with some versions of the Code Red IDE. For example with NXP LPC13xx parts, connecting more than once to the MCU with vector catch enabled can lead to the part ID being incorrectly read - which can again cause debug connections to fail This patch adds an alternative part ID for LPC1343. With this patch "program" command works fine for flashing. Change-Id: I8632e898a4c33102455925d25715b4f4edfa1d97 Signed-off-by: Jakub Kubiak <jakub@kubiak.es> Reviewed-on: http://openocd.zylin.com/2782 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-26niietcm4: support for NIIET's Cortex-M4 microcontrollersBogdan Kolbov
This adds docs, example config, flash driver. Driver is only supports K1921VK01T model for now. Change-Id: I135259bb055dd2df1a17de99f066e2b24eae1b0f Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru> Reviewed-on: http://openocd.zylin.com/3011 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-23efm32: remove duplicate part name decoding.Karl Palsson
The probe and info methods had duplicate sections decoding family names to generate a human friendly part name. Extract this to a common helper. Change-Id: I4c6309d83c601e154b7c14ad9c15c53854ee1e98 Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/2932 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-23efm32: basic Happy Gecko target supportKarl Palsson
Basic basic support to get running, magic numbers taken from revision 0.90 of the reference manual. Signed-off-by: Karl Palsson <karlp@tweak.net.au> Change-Id: Iff6ab94d30698f056ef09f7a856b7285fed8f441 Reviewed-on: http://openocd.zylin.com/2931 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-23jtag: commands: save a pointer to list tailFelipe Balbi
By saving a pointer to the tail of the list, we don't need to traverse the entire command queue before we're able to append an item to it. With this patch, I see a 10% improvement when using the embedded XDS100v2 on AM437x IDK board to load a 4MiB binary (linux zImage) to DDR with load_image. IOW, we went from ~305kB/sec to ~336kb/sec. Change-Id: Idb55d49f0d0106043374ab520b2f3b6b32f2c50f Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-on: http://openocd.zylin.com/2709 Tested-by: jenkins Reviewed-by: Stian Skjelstad <stian@nixia.no> Reviewed-by: Daniele Emancipato <daniele12457@hotmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-20svf: fix progress reporting switch behaviourPaul Fertser
The svf_progress_enabled variable is global, hence its lifetime is not limited and it retains the value from the previous run. Fix this by explicit assignment. Change-Id: Id6f4fa88f39521606342a37f6876a0948ac5406e Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3111 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-20svf: fix off-by-one error in line numbers as output to userPaul Fertser
This makes SVF error output match actual line numbers in the file processed. Change-Id: I1fa4b9d0891e4358b7beada516945d5331ebe182 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2945 Tested-by: jenkins
2015-11-20Kinetis: suppress false alarms "MCU is secured"Tomas Vanek
Kinetis driver checks MDM STAT register to detect secured state of MCU. An unsecured clean device typically triggered a huge fat alarm message. Now when driver detects secured state it tries to halt MCU and then re-reads status register. Command "mdm mass_erase" used to deassert reset when finished and MCU started looping in hard fault - WDOG reset cycle. Now "reset halt" is issued. Clean flash is not run after mass_erase. Change-Id: I23f393509fbd8751d44ffc744ff2d67f1074f74e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3010 Tested-by: jenkins Reviewed-by: Thomas Schmid <thomas@rfranging.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-20flash: at91samd: flash write code cleaningTomas Vanek
SAMD driver suffered from following problems: 1) Flash was erased as an integral part of flash write. It was not documented so with usual workflow it resulted in erasing flash twice (and reducing flash lifespan) and in almost double flashing time. 2) Sector erase was silently skipped if "is_erased" flag was set. "is_erased" logic was not reliable, e.g. when a row write was aborted after successful write of some pages, sector was still considered as erased. "is_erased" flag could not cope with flash writes from a user program. 3) Writing of a block with start address unaligned to a flash page resulted in failed assert and OpenOCD abort. 4) Disabling cache in bit 18 of 16-bit halfword never worked. MCU implements cache invalidate in hardware so there is no need to take care about. This bug was reported by Tony DiCola. New code does not erase flash in write operation. Instead it traditionally relies on erasing flash beforehand. "is_erased" logic and cache disabling is completely removed. It simplifies write procedure a lot and flash write is now faster. The change partly solves ticket #109 SAMD/SAM4L driver doubles flash erase. Change-Id: I582b497d01a351575533a1f8c9810a4413be0216 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3045 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-20flash: at91samd: Add SAML21 variant B device support and fix SAMC20/SAMC21Andreas Loehre
This adds support for the Atmel SAML21 variant B parts. There is minimal change between the two variants, but in variant B the automatic page write which the at91samd flash driver relies on to be enabled is disabled by default. With this patch the write row function will now issue a page write command after each of the four pages in the row if the MANW (manual write) bit is set. This also fixes flash write for the SAMC20/SAMC21 devices which have the MANW bit set by default as well. I have also moved the device ID (DID) register bitfield extraction from the find_part into helper macros. These can be used in the future if there are more workarounds for specific devices. Tested (programming) on: ATSAML21-XPRO ATSAML21-XPRO-B SAMC21 Xplained Pro SAMD21 Xplained Pro SAMD20 Xplained Pro Change-Id: I401a8aa1efd64730840c0d62cf49a1e880ea5900 Signed-off-by: Andreas Loehre <alohre@gmail.com> Reviewed-on: http://openocd.zylin.com/2903 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2015-11-20jtag: cmsis-dap: Issue disconnect before reconnectingTomas Vanek
cmsis-dap protocol has both DAP_Connect and DAP_Disconnect commands. Logically if cmsis_dap_swd_switch_seq() calls DAP_Connect in connected state it should call DAP_Disconnect first. Doing so surprisingly solves problems on Atmel EDBG with target SAMD/R/L/C. Without this change SWD communication breaks after reset run/halt in config "reset_config srst_only" and reconnect trials repeatedly fail with "SWD ack not OK: 0 JUNK" Change-Id: Ie951098d5e0c83f388e2df414608aaabec2135c9 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3098 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-20at91samd: handle reset run/halt in DSUTomas Vanek
Atmel introduced a "Device Service Unit" (DSU) that holds the CPU in reset if TCK is low when srst (RESET_N) is deasserted. Function is similar to SMAP in ATSAM4L, see http://openocd.zylin.com/2604 Atmel's EDBG adapter handles DSU reset correctly without this change. An ordinary SWD adapter leaves TCK in its default state, low. So without this change any use of sysresetreq or srst locks the chip in reset state until power is cycled. A new function dsu_reset_deassert is called as reset-deassert-post event handler. It optionally prepares reset vector catch and DSU reset is released then. Additionally SWD clock comment is fixed in at91samdXX.cfg and clock is lowered a bit to ensure a margin for RC oscillator frequency deviation. adapter_nsrst_delay 100 is commented out because is no more necessary after http://openocd.zylin.com/2601 Change-Id: I42e99b1b245f766616c0a0d939f60612c29bd16c Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2778 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-13target: cortex_a: add deinit_target handler to free memoryPaul Fertser
Tested with Valgrind accesing a Pandaboard. Change-Id: I51bba044974ecfc4d418998816d44a8563264123 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3101 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-11flash/nor/xmc4xxx: Loosen checks for XMC4500Andreas Färber
According to Infineon, XMC4500 EES AA13 with date codes before GE212 - as seen on an XMC4500 General App Kit - had a zero SCU_IDCHIP register. Handle this by extending our checks to not error out on zero SCU_IDCHIP and by printing a useful info string in that case. Change-Id: Ic2d641a314627dd5a1ff775a0113999191b95e3d Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/2751 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
2015-11-11flash: New driver for XMC4xxx microcontroller familyJeff Ciesielski
This is a complete flash driver for the Infineon XMC4xxx family of microcontrollers, based on the TMS570 driver by Andrey Yurovsky. The driver attempts to discover the particular variant of MCU via a combination of the SCU register (to determine if this is indeed an XMC4xxx part) and the FLASH0_ID register (to determine the variant). If this fails, the driver will not load. The driver has been added to the README and documentation. Tests: * Hardware: XMC4500 (XMC4500_relax), XMC4200 (XMC4200 enterprise) * SWD + JTAG * Binary: 144k, 1M Note: * Flash protect only partly tested. These parts only allow the flash protection registers (UCB) to be written 4 times total, and my devkits have run out of uses (more on the way) Future Work: * User 1/2(permalock) locking support via custom command * In-memory flash loader bootstrap (flashing is rather slow...) Change-Id: I1d3345d5255d8de8dc4175cf987eb4a037a8cf7f Signed-off-by: Jeff Ciesielski <jeffciesielski@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/2488 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-10flash: driver for Atmel SAMV, SAMS, and SAMEMorgan Quigley
This is a driver for the Atmel Cortex-M7 SAMV, SAMS, and SAME. I started with the at91sam4.c driver and then restructured it significantly to try to simplify it and limit the functionality to just a flash driver, as well as to comply with the style guide. Change-Id: I5340bf61f067265b8ebabd3adad45be45324b707 Signed-off-by: Morgan Quigley <morgan@osrfoundation.org> Reviewed-on: http://openocd.zylin.com/2952 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2015-11-10cfi: Fix fallback to memory writesEsben Haabendal
Change-Id: I2d09139b95ff62c62a0b071584e85a87494ed313 Signed-off-by: Esben Haabendal <esben@haabendal.dk> Reviewed-on: http://openocd.zylin.com/3095 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-07target: cortex_a: do not create new register cache every resetPaul Fertser
Commit 68101e67ac16bdead3bd6d48cbe0a2bfd63aac02 introduced a regression which resulted for ever-growing registers list (as output by "reg" command), its contents were doubled every reset (actually, every examination). Change-Id: Ie3409c795160a2fc840a5e8a892928df0bcc0c57 Reported-by: Daniele Emancipato <daniele12457@hotmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3100 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-07Cortex A/R : Allow interrupt disable during single-stepEvan Hunter
Example usage: cortex_a maskisr on cortex_a maskisr off cortex_r maskisr on cortex_r maskisr off Change-Id: I799288d9b848a06f561ba29ec1eb8e5eeace5685 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2876 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-05flash/nor/spi: Add GigaDevice gd25q16c/32c/128c flash supportMahavir Jain
Change-Id: I44052fd3467d7e0bbdc038b815204e39fa499684 Signed-off-by: Mahavir Jain <mjain@marvell.com> Reviewed-on: http://openocd.zylin.com/3029 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-05armv7a: correct calculation of ttbr0_maskMatthias Welwarsky
This patch brings the calculation of the address ranges handled by ttbr0 and ttbr1 registers in line with ARM DDI 0406C, Table B3-1 Change-Id: Ib807c4b1cb328a6f661e1a0898e744e60d3eccac Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3006 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-05armv7a: re-read ttb information if ttbcr changesMatthias Welwarsky
If ttbcr is changed after the debugger has examined a target for the first time, address translations may fail. This problem does not show up with Linux because it doesn't use ttbr1, but it shows with other OS that use this feature. If the debugger connects to the target while it's in u-boot, all address translations will fail after the OS has booted and the target can not be debugged. This patch reads the ttbcr in armv7a_mmu_translate_va() and compares it a cached value. If a difference is detected, armv7a_read_ttbcr() is called to re-parse the ttb configuration and update the cache. Change-Id: I1c3adf53ea9d748a0e1e3091d9581e5c43ed64e8 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3005 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-05Kinetis: properly pad flash section writesTomas Vanek
kinetis_write() with byte count not divisible by prog_section_chunk_bytes computed wrong wc and therefore paded section chunk by some random data instead of 0xff Change-Id: Ic7c66d8a3ceacda9e611e98b9fbf943b8001774b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2994 Tested-by: jenkins Reviewed-by: Thomas Schmid <thomas@rfranging.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-05Kinetis: Disable watchdog on Kx devices when programming.Thomas Schmid
Kx devices with FTFA flash need the watchdog disabled when programming. I tried to keep overhead as small as possible and re-use registers that were already inquired (e.g. sim_sdid). Change-Id: Ibc29a26ec34102d78a6c3920dd16f63e134a8f6f Signed-off-by: Thomas Schmid <thomas@rfranging.com> Reviewed-on: http://openocd.zylin.com/2986 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-03helper/options: Use OPENOCD_SCRIPTS dir if set.Jonathan Larmour
This makes it easier to relocate the install tree of OpenOCD from where it was originally built (for example, if put onto a different machine), without having to change scripts or add something to the command line every time. Change-Id: Ia5edf0eba166f7a999f267bd6a92402dab9b399e Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com> Reviewed-on: http://openocd.zylin.com/3004 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-16 20:51:48 +0000