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2013-04-02arm_adi_v5: fix mem_ap_read_buf_u32() JTAG nastiness..mike brown
Moved JTAG code out of transport-neutral file (arm_adi_v5.c) into transport specific file (adi_v5_jtag.c). Added ap_block_read to dap_ops interface (arm_adi_v5.h) to support the move. Change-Id: I796d3984f138aad052b97c77ac9c12ffd1158f74 Signed-off-by: mike brown <mike@theshedworks.org.uk> Reviewed-on: http://openocd.zylin.com/1277 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15target: fix broken Cortex-R4 supportSpencer Oliver
This regression was caused due to the recent addition of R4 support and the removal of the bulk_write_memory handler. Change-Id: Ide692737f235c0e9906becb6f3502ba52c5907aa Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1246 Tested-by: jenkins
2013-03-15target: Retire target_bulk_write_memory()Andreas Fritiofson
The only caller was arm_nandwrite(). Replace that call with target_write_buffer() instead, which in turn may end up calling the same bulk_write_memory target API function. Change-Id: If34c7474df5cf14af3b732fb4774816818f28e79 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1214 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15target: Add default implementation of bulk_write_memoryAndreas Fritiofson
Remove dummy implementations from all targets except arm7_9 and mips, which are the only ones with real implementations. Replace with a single default implementation simply calling target_write_memory(). Change-Id: I9228104240bc0b50661be20bc7909713ccda2164 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1213 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15arch: Added ARMv7R and Cortex-R4 supportEvan Hunter
Rewrite to merge Cortex-A and Cortex-R code Change-Id: I4541557980d43d1bba6e8d1bfeb04f536ed25a00 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/358 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15adi_v5: search for Debug and Memory AP supportEvan Hunter
Adds dap_find_ap() function. Change-Id: I6643025624009b12d4936de67a605da52c07be49 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/909 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15cortex_a : optimize apb read/write access.Evan Hunter
Rewrite: Adheres more closely to 'fast read/write' examples in TRM. up to 50x faster Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/903 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove read_memory_impAndreas Fritiofson
Change-Id: Idc6ef3b075ccbb5945df8fea746011cb17175d8f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1219 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove write_memory_impAndreas Fritiofson
Change-Id: I5d933bc19443bba8a0193c90471fdd0614324a92 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1218 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove soft_reset_halt_impAndreas Fritiofson
Change-Id: I12c907584ef73de570eba2dcfeb8477cabc6098f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1217 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-06target: use common target_name to access target::cmd_name memberSpencer Oliver
Change-Id: I203b89ef25a072c3b00b504483d5f2a83477fad6 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1182 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-03-05Move back off timer to target structMathias K
Move the global target back off timer to the target struct. This will fix the wrong error handling with multi target devices like smp systems. Change-Id: Ia327182ed5d13ca87323700017a8c40ecc6b25a3 Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/1179 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-03-05Add the target name to debug output for better understanding and error ↵Mathias K
identification. Change-Id: I1054debea6cd3a6548aadeae2d84000a0039814e Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/1178 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-02-26gdbserver: use common hexify/unhexify routinesSpencer Oliver
Change-Id: I9989b625666e9c60ec9867cf6f4d94f41c998c3f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1105 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2013-02-25target: hla correctly use target eventsSpencer Oliver
Because we were always running using target state TARGET_RUNNING target algorithm's were a bit verbose compared to other targets. This brings the hla target inline with the other targets. Change-Id: I3a257fdc878b87660fac8b5eca22b421eee5b349 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1134 Tested-by: jenkins
2013-02-25armv7m: update to use correct register core_cacheSpencer Oliver
The was missed when the armv7m was moved over to using the std arm core_cache, probably because it is disabled by default. Change-Id: I2f5a18ef6dd783b36e8c29f4c52379104bda4583 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1138 Tested-by: jenkins
2013-02-02armv7m: use ARM_MODE_THREAD core mode for algoorithm'sSpencer Oliver
This makes sure we are using privileged mode when executing any loaders. Change-Id: I18bf32ec92e1c76a66ab25e3712652bc3650b332 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1108 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: restore core mode after executing algorithmSpencer Oliver
Make sure we restore the core mode after executing any algorithm. We also now check that we actually need to swap the core mode, we may already be in the correct mode. Change-Id: Ia48af2c108e0f9868aae241bf25f60323503f092 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1107 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic arm read/write_core_regSpencer Oliver
Change-Id: I0c15acc1278d2972269d294078495e6b069c830b Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/969 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic register core_cacheSpencer Oliver
This removes the armv7m::core_cache and uses the generic arm::core_cache. Change-Id: If854281b31486cea8be005008f6a71a691b4c208 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/968 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: remove unused armv7m_regtypeSpencer Oliver
This simplifies the armv7m_core_reg structure ready for the move to using the generic struct arm_reg. Change-Id: I8edb9d77cc54965d49cd2e754568ebcea4cf6964 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/967 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic arm::core_modeSpencer Oliver
To simplify things change over to using the generic core_mode struct rather than maintaining a armv7m specific one. Change-Id: Ibf32b785d896fef4f33307fabe0d8eb266f7086f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/966 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-01-27hla: enable DWT component and fix watchpointsSpencer Oliver
The makes sure the DWT component is always enabled so that watchpoints work as expected. This does need merging into the existing cortex_m logic, however at the moment this is non trivial. Change-Id: Ic6cccd1badb51f70a2ca8ea9ab6923788a94c1bf Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1122 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-01-02hla: support setting DCB_DEMCR on resumeSpencer Oliver
This is only minimal support to enable use to catch a Hard Fault in the stm32l flash bootloader. Change-Id: I21d6a11893e2f1d173ebff1a651d6f52bf6eec32 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1103 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: jenkins
2012-12-23hla: add ability to configure read/write buffer sizeSpencer Oliver
Other adapters (TI ICDI) that use this driver can use a larger read/write buffer size than the original stlink could. Change-Id: I9beb7748049097cbe29a2340799c450bd74e199d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/948 Tested-by: jenkins
2012-12-23hla: fix watchpoints not being setSpencer Oliver
Watchpoints were not being enabled when the hl adapter target was resumed. This effects both stlink and icdi interfaces. Change-Id: Ia9f8a9415be97a467cd099b63b6bc9f7f37d0c0d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/931 Tested-by: jenkins
2012-12-23stlink: rename stlink cmd namesSpencer Oliver
As part of the switch to using the hla for the stlink interface we rename the cmds to a more generic name. Update scripts to match new names. Also add handlers for deprecated names. Change-Id: I6f00743da746e3aa13ce06acfdc93c8049545e07 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/921 Tested-by: jenkins
2012-12-23target: add deprecated target name supportSpencer Oliver
This enables us to change the target name without breaking any target scripts. Change-Id: I635f961e573264d3dab2560f3a803ef1986ccfde Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/919 Tested-by: jenkins
2012-12-11mips_m4k: Fixed mips_m4k_resume code for smp targetsKamal Dasu
Fix for bug introduced in in mips smp support code in the resume logic that is checking for wrong return value. Change-Id: Ice3e0069f936b556fecc338ccc12ddba38deeaf6 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1048 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09cortex_a: Fix target entry state route.Evan Hunter
If target is disabled at init, then is examined using 'arp_examine', it can get to cortex_a8_poll with the target state being unknown. Change-Id: Ifffb345bf971d275d2eb1912648b29f0a75f6ccc Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/954 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09mips_m4k: Added SMP debug support for mips architecturesKamal Dasu
This change adds smp debug support for mips platforms. The change leverages the exiting gdb smp support as mentioned in the OpenOCD documentation for using gdb in smp environemnt. Added commands smp_on, smp_off, smp_gdb to control the smp mode. The implementation also provides a way to send Jc packet and toggle the gdb display core context as well. Change-Id: I0835a5aed1844b6ebf8291582912f20695346003 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/937 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09mips_ejtag: Adding EJTAG 4.x and 5.x as valid versionsKamal Dasu
This is a minor change to log EJTAG version 4.x and 5.x as valid versions when debug log is enabled. Change-Id: Ie20458d033c6d22842cb4a31b56765d4ba2ff123 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/936 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-30arm: Mis-aligned data issue fix.Jason Moehlman
Fixes issue with big endian hosts and mis-aligned data on some hosts. Fixes unaligned access exception on hosts that do not support unaligned access when debugging some arm targets. Signed-off-by: Jason Moehlman <jmoehlma@linux-software.com> Change-Id: I6bc6fb1b3c3565b256674b9ef43ed2afd14f5178 Reviewed-on: http://openocd.zylin.com/996 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-11-16mips: patch mips32_pracc_exec_write()Salvador Arroyo
No function writes to MIPS32_PRACC_PARAM_IN addresses and probably has no much sense. Any attempt to write to those addresses should be an error. Change-Id: Iebea5fa9954e2cd56ad34976dd7d25009c6e6388 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/975 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_read_regs() codeSalvador Arroyo
Current code needs 101 pracc accesses for this function, this code needs 12 less. There is a singularity in this code, is the only function that restore a register from param out instead from pracc stack. Obviously the register was previously stored at param out. This save 2 pracc accesses. Change-Id: Ie95b6f983a3198dafc0eab2dd5acc11f871a8d83 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/958 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_write_regs() code.Salvador Arroyo
All the the loads are done with lui and ori instructions, there is no need to save any register, they will be overwritten. Like in the previous patch, for speed optimization in write code, same instructions can be saved if the lower half word or the upper half word is 0. If the lower half word is 0, it can be loaded with only a lui instruction. If the higher half word is 0 it can be done with an ori instruction with register 0. This code saves 10 pracc accesses at a minimum, and 40 at a maximum, obviously if register 2 to 31 are 0 or a half word is 0 Current code needs 91 pracc accesses. Change-Id: I892c5b440191d0c7a474c96845d41c373b7fc637 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/957 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
2012-11-16mips: optimize write code for speedSalvador Arroyo
All the writes are done by the new function mips32_pracc_write_mem_generic(). The code is similar to the read generic code. The reuse of register 15 as memory base address saves 3 pracc accesses. The first write takes 13(12) pracc accesses and for additional writes 3(2). Loading miniprograms should take 25% less time and loading fastdata transfer handler code should be over 2x faster. Change-Id: Ia3b24ba084af33be99da19f00a7fd4d1b291f350 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/956 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize read code for speedSalvador Arroyo
Really nothing new that not explained in previous patches. The code is expanded as needed, there are no loops in pracc code. For the first value pracc accesses are reduced from 39 to 16 and for aditional values from 10 to 3. dump_image should work around 3x faster. Change-Id: I37c9b13395c09eb52a91f10cdb6cbaedef8ab98b Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/955 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_read_u32() functionSalvador Arroyo
This function is highly optimized, there is not much to improve. Loading the base address for pracc access with the new defined MIPS32_PRACC_BASE_ADDR saves one instruction. The memory address is loaded in too steps. First the upper address is loaded. The lower address is passed as an offset in the memory load instruction. The offset is signed, if the lower address is in the range of 0x8000 to 0xffff the offset is a negative value, and the upper address must be incremented by 1. Pracc accesses are now 12 instead of 14. Change-Id: I286945b240ed5c5d5cc540780a41a8a5fa075da3 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/952 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize CP0 read/write codeSalvador Arroyo
MIPS32_PRACC_BASE_ADDR is defined as 0xFF200000. Now is possible to load the base address with a lui instruction and only one pracc access. Offsets to the pracc code addresses are defined to simplify the code and probably make it a bit more readable or self-explained. Change-Id: I853dd2d7fad52745931cc6e6be68c0ae156d897e Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/951 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
2012-11-16mips: code clean up in mips_m4k_debug_entry() functionSalvador Arroyo
The function mips_ejtag_read_debug() is defined in mips_ejtag.c and is called only by mips_m4k_debug_entry() for reading the CP0 debug register. The comment in this function is obviously wrong. There is a generic function to read CP0 registers with similar code. A call to mips32_cp0_read() should work in the same way. The purpose of reading the debug register is to test if the DSS bit is set and clear the SSt bit. It is faster and easier if the SSt bit is cleared without any check. Remark: DSS bit set only means that a debug single-step exception ocurred, but it is not possible to step over a sdbbp instruction, in this case DSS will not be set and the SSt bit not cleared by code. Resume command at another address will step, so really the behavior is not the same. Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/950 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips_ejtag_step_disable() codeSalvador Arroyo
The code is a bit large compared to mips_ejtag_step_enable(). With the mips32 xori instruction the code can be reused. The number of pracc accesses are reduced from 18 to 7. Change-Id: If3974ebd64da4461c22b089796646990e68e1b72 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/944 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-06target: add async algorithm timeoutSpencer Oliver
An issue was observed when using an async algorithm with a target that had not been previously reset beforehand. The target would enter a infinite loop within target_run_flash_async_algorithm. Add a timeout that will at least prevent this issue from happening. and also suggest the user resets the target. Change-Id: I5277e0d64e252d3d353e8d5bc9889a37fdc63060 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/949 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2012-11-06ARM v4/v5 target files: mrc and mcr help information is incorrect.Karl Kurbjun
The order of the mrc/mcr command matches the ARM Architecture Reference Manual. This patch corrects the help information for mrc/mcr. Change-Id: I1f0e6a628a3644124591a6aa291b8a58cfd93b44 Signed-off-by: Karl Kurbjun <kkurbjun@gmail.com> Reviewed-on: http://openocd.zylin.com/914 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-06cortex: autostep correctly handle user breakpointSpencer Oliver
If we halt due to a breakpoint make sure that we do not remove it during a step, only remove breakpoints we have created. Change-Id: I060168e54e53637d4fbf3cbcf62072efdb353807 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/947 Tested-by: jenkins
2012-11-06cortex_m: Fix single stepping will not return to debug mode sometimesPeter Horn
This occurs when stepping past a breakpoint on a even address with maskisr option set to auto With -d3 the following log message appears in this case: "Debug : Interrupt handlers didn't complete within time, leaving target running" Cause : Given a breakpoint is set on the lower half word and the PC is on the upper half word. When another breakpoint is now set on the current PC then resuming the core will not result in a break on the newly set breakpoint. This has been observed on a STM32F1x, STM32F2x (CM3) but not on a STM32F0x (CM0). It's not clear if this is a STM32F1/F2 only or a general CM3 problem. Change-Id: I384813f3bfdf935373b5e23cdb2d7f243c70cc00 Signed-off-by: Peter Horn <peter.horn@bluewin.ch> Reviewed-on: http://openocd.zylin.com/864 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-05cortex_m: fix define formattingSpencer Oliver
Change-Id: Ibdec882b2afc7e16f2361f86715463e030a54964 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/963 Tested-by: jenkins
2012-11-05rtos: Add FPU detection to ChibiOS/RTMatthias Blaicher
The stacking of ChibiOS/RT depends on the usage of an FPU. If the FPU is enabled the FPU registers are also saved on context switch. This patch adds automatic detection of FPU for armv7m targets. Note: With this patch, openocd will only output an error message warning that the FPU is enabled. For further FPU support, the correct stacking information also needs to be added. Change-Id: I0984cbd9180f247ba2fa610e74a6413cc54239ea Signed-off-by: Matthias Blaicher <matthias@blaicher.com> Reviewed-on: http://openocd.zylin.com/961 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-10-31Ensure Cortex-M reset wakes device from sleep (wfi/wfe)Evan Hunter
Change-Id: Idb52ca3123bb3e2f7863ba1b82ac9b176d7cb094 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/833 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-10-28gdb: use strncmp rather than strstrSpencer Oliver
All the packets received will be at start of the packet buffer, so use more efficient strncmp. Change-Id: Ib9c45d8f53425367006b1f880c1bde27f03a6cf9 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/932 Tested-by: jenkins Reviewed-by: Matthias Blaicher <matthias@blaicher.com> Reviewed-by: Peter Stuge <peter@stuge.se>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-20 19:10:43 +0000