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made two functions into static, since they are not required by anything external
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added an attempt to use the non-reseting halting sequence. if it fails, then the full sequence will be attempted. this makes things a bit faster most of the time.
changed the location of a function, avoiding a forward def
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emacs is awesome.
replace-regexp RET [ ]+$ RET RET
and it's done
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added an alternative way to enter debug mode, which does not require restarting the chip.
this will not always work, but in general it will (failure 0.3%), and failure is not a dramatic issue, simply have to use the full sequence.
the user can only access "halt", which uses the full sequence, so the user should not have any problems.
restarting the chip requires reconfiguring the flash module. the doc is very poor, so i'd rather have the two methods, and live with the 0.3%.
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sometimes the master tap will be enabled, since tap switching is required during halt/lock/unlocking procedures.
now irscan handles this, avoiding unnecessary warnings and preventing errors.
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got new info regarding setting the chip to debug mode, and locking/unlocking flash memory.
the newer implementation is a bit slower, but always works.
the previous implementation would randomly (as once every 25k-70k times) get the chip into a state where the freescale tool would be necessary. this is fixed now.
added functions to play around with the jtag state machine. they are not the happiest, but are necessary to be able to execute the halting/locking/unlocking sequences.
Conflicts:
src/target/dsp5680xx.c
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the user can execute halt, but no enter_debug_mode. modified the error handling to suite this.
the new implementation of unlocking will use enter_debug_mode, and should not get the same errors as the user would, because not being able to enter debug mode is actually success when checking for locked flash.
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crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.
also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.
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the master tap has a 4 bit irlen
changed the instructions to be 4 bit, ie, removed the zeros.
it makes it clearer to interpret.
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it returned ERROR_OK even though it actually failed.
this made the Tcl interface report success, though it had not succeeded.
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i had started my code from dsp5683xx, i renamed a bunch of stuff to names i consider to be better.
i believe no one is using this code, so nobody should be affected. (it's not too late to do this change)
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Function mips_m4k_write_memory() does endianess byte swap,
but this procedure break one byte access (temporary array
overwrites content in buffer).
As a fix, this endianess swap and buffer affecting
is preformed only on hword and word accesses (not on byte access).
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Pprogram that loads another program into memory is actually writing the
D- side cache.
The instructions it has loaded can't be executed until they reach the
I-cache.
After the instructions have been written, the loader should arrange to
write back any containing D-cache line and invalidate any locations
already in the I-cache.
For the MIPS Architecture Release2 cores, we can use synci command
that does this job.
For Release1 we must use "cache" instruction.
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This patch adds MIPS32 CP0 coprocessor R/W routines,
as well as adequate commands to use these routines via
telnet interface.
Now is becomes possible to affect CP0 internal registers
and configure CPU directly from OpenOCD.
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For all architectures we use distinct common magic number,
and this should be a uint32_t type.
Otherwise, comparison with macros will yield compilation
warning.
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jtag_execute_queue() is executed as a part of mips_ejtag_drscan_32().
No need for this to be done before - removed for optimisation.
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This reverts commit d567df02b9f3e7d2e7e78b3c2907ecad9aa4bbd4.
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a counter was incorrectly set
when i added the macros i incorrectly called them.
fixed that.
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before doing anything with the flash module (FM) the clock divider must be set.
if erase_check was the first thing done with the FM after reset then an error would be generated because the clk divider was not set.
now erase_check sets the clk divider.
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reorganized code to get rid of compiler warnings
the warning were related to allignment, i do not get these warning on my build system (i've tried setting the compiler flag but it doesn't work, still working on why) so i cannot detect them (yet.)
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This corrects two issues found with openocd.
d7f71e7fe9645fa8c3f88cf6fc9ad438aa6708f3 removed some code that was
being used.
The above then caused even more code to get removed by commit 1cfb2287a67c1f78b76583b2e5ed83ca3560b0d5.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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The patch fix comparison of target data on the host by using
target_buffer_get_u16() to transform current_instr to
_host_ endianess before comparison.
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This patch extends the cortex_m3 maskisr command by a new option 'auto'.
The 'auto' option handles interrupts during stepping in a way they are
processed but don't disturb the program flow during debugging.
Before one had to choose to either enable or disable interrupts. The former
steps into interrupt handlers when they trigger. This disturbs the flow during
debugging, making it hard to follow some piece of code when interrupts occur
often.
When interrupts are disabled, the flow isn't disturbed but code relying on
interrupt handlers to be processed will stop working. For example a delay
function counting the number of timer interrupts will never complete, RTOS
task switching will not occur and output I/O queues of interrupt driven
I/O will stall or overflow.
Using the 'maskisr' command also typically requires gdb hooks to be supplied
by the user to switch interrupts off during the step and to enable them again
afterward.
The new 'auto' option of the 'maskisr' command solves the above problems. When
set, the step command allows pending interrupt handlers to be executed before
the step, then the step is taken with interrupts disabled and finally interrupts
are enabled again. This way interrupt processing stays in the background without
disturbing the flow of debugging. No gdb hooks are required. The 'auto'
option is the default, since it's believed that handling interrupts in this
way is suitable for most users.
The principle used for interrupt handling could probably be used for other
targets too.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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This reverts commit ff640f197a9a343b2f3ed10e9174e35282334e8c.
Original patch reverted as Author's name was incorrectly set.
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In order to compare data read from the target with some marcros or data
defined on the host, we must transform this read data from target
endianess to host endianess.
target_read_memory() gets bytes from target to the host, but keeps them in _target_
endianess. This is OK if we just want to temporary keep this data on the
host, like keeping breakpoint->orig_instr. But if we want to use this
data for any ispections and comparisons on the host side, we must
transform it to _host_ endianess, by using target_buffer_get_u32()
function.
Currently this transformation is missing, and check current_instr ==
MIPS32_SDBBP will never pass if target and host endianess differ,
because current_instr will be kept in _target_ endianess and
MIPS32_SDBBP will be kept in _host_ endianess,
The patch fix this issue by using target_buffer_get_u32() to transform current_instr to
_host_ endianess before comparison.
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Use "git revert <commit>" to revert this commit, then build and
repair and post patch to the mailing list.
Warnings generated with:
nios2-elf-gcc (GCC) 3.4.6 (Altera Nios II 9.1 b222)
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_upper_data':
openocd/src/target/dsp5680xx.c:252: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_lower_data':
openocd/src/target/dsp5680xx.c:268: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_pc_store':
openocd/src/target/dsp5680xx.c:508: warning: dereferencing type-punned
pointer will break strict-aliasing rules
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_read':
openocd/src/target/dsp5680xx.c:736: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:737: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write_8':
openocd/src/target/dsp5680xx.c:823: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write':
openocd/src/target/dsp5680xx.c:938: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:941: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_f_wr':
openocd/src/target/dsp5680xx.c:1355: warning: cast increases required
alignment of target type
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the code was making assumptions about the endianness of the host.
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use a more specific global variable name than "context", which
can easily conflict with other things.
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This patch extends the cortex_m3 maskisr command by a new option 'auto'.
The 'auto' option handles interrupts during stepping in a way they are
processed but don't disturb the program flow during debugging.
Before one had to choose to either enable or disable interrupts. The former
steps into interrupt handlers when they trigger. This disturbs the flow during
debugging, making it hard to follow some piece of code when interrupts occur
often.
When interrupts are disabled, the flow isn't disturbed but code relying on
interrupt handlers to be processed will stop working. For example a delay
function counting the number of timer interrupts will never complete, RTOS
task switching will not occur and output I/O queues of interrupt driven
I/O will stall or overflow.
Using the 'maskisr' command also typically requires gdb hooks to be supplied
by the user to switch interrupts off during the step and to enable them again
afterward.
The new 'auto' option of the 'maskisr' command solves the above problems. When
set, the step command allows pending interrupt handlers to be executed before
the step, then the step is taken with interrupts disabled and finally interrupts
are enabled again. This way interrupt processing stays in the background without
disturbing the flow of debugging. No gdb hooks are required. The 'auto'
option is the default, since it's believed that handling interrupts in this
way is suitable for most users.
The principle used for interrupt handling could probably be used for other
targets too.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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So far image_load command tries to load ELF binaries to address
discovered by reading p_paddr member of a Program header of an ELF
segment.
However, ELF specifications says for p_paddr : ...Because System V
ignores physical addressing for application programs, this member has
unspecified contents for executable files and shared objects.
ARM ELF specifiaction goes even further, demanding that this member
be set to zero, using the p_vaddr as a segment load address.
To avoid the cases to wrong addr where p_paddr is zero,
we are now using p_vaddr to as a load destination in case that *all*
p_paddr == 0. Basically, this patch re-implements the approach present in
BDF's elf.c, which is used by GDB also (so that we can be consistent).
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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as we introduce swd and jtag as two transports, we want
to start up with a new transport folder to organize the
code a bit.
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