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DCC downloads should be enabled for any self repecting
openocd config file for arm7/9. Print out note about
it otherwise.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Allow targets to run checks post reset. Used to check
that e.g. DCC downloads have been enabled.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Use the correct bitfield to specify the register whose
top halfword gets replaced.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Use correct tcl syntax to throw exception.
the syntax is "return -code error" not "return -error"
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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- add target_to_mips32 and target_to_m4k to match test of codebase.
- mips32_arch_state now shows if processer is running mips16e isa.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Usage messages should use the same EBNF as the User's Guide;
no angle brackets. Be more complete too ... some params were
missing.
Don't use "&function"; its name is its address.
Unrelated: fix typo in one "target.c" usage message.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Usage syntax messages have the same EBNF as the User's Guide;
there should be no angle brackets in either place.
Uupdate some helptext to be more accurate.
Don't use "&function"; functions are like arrays, their address
is their name.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Usage syntax messages have the same EBNF as the User's Guide;
there should be no angle brackets in either place.
Fix the User's Guide to say where the magic CP15 bits are defined;
and add comments in case someone provides mcr/mrc methods.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Deprecate the "pass an instruction opcode" flavor of cp15
access in favor of the "arm mcr ..." and "arm mrc ..."
commands, which offer fewer ways to break things.
Use the same EBNF syntax in the code as for the user's guide.
Update User's Guide to say where to find those magic values
(which table in the ARM920 TRM).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Deprecate the "pass an instruction opcode" flavor of cp15 access
in favor of the "arm mcr ..." and "arm mrc ..." commands, which
offer fewer ways to break things.
Use the same EBNF syntax in the code as for the user's guide.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Usage syntax messages have the same EBNF as the User's Guide;
there should be no angle brackets in either place.
Uupdate some helptext to be more accurate.
Fix the User's Guide in a few places to be more consistent (mostly
to use brackets not parentheses) and to recognize that parameter may
be entirely optional (in which case the command just displays output,
and changes nothing). Also reference NXP, not Philips, for LPC chips.
Don't use "&function"; functions are like arrays, their address
is their name.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Provide helptext which was sometimes missing; update some of it
to be more accurate.
Usage syntax messages have the same EBNF as the User's Guide;
there should be no angle brackets in either place.
Fix the User's Guide in a few places to be more consistent (mostly
to use brackets not parentheses) and to recognize that parameter may
be entirely optional (in which case the command just displays output,
and changes nothing). Also reference NXP, not Philips, for LPC chips.
Don't use "&function"; functions are like arrays, their address
is their name. Shrink some overlong lines.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Provide helptext which was sometimes missing; update some of it
to be more accurate.
Usage syntax messages have the same EBNF as the User's Guide;
there should be no angle brackets in either place.
Don't use "&function"; functions are like arrays, their address
is their name. Shrink some overlong lines, remove some empties.
Add a couple comments about things that should change: those
extra TCK cycles for MEM-AP reads are in the wrong place (that
might explain some problems we've seen); the DAP command tables
should be shared, not copied.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Provide helptext which was sometimes missing; update some of it
to be more accurate.
Usage syntax messages have the same EBNF as the User's Guide;
no angle brackets in either place.
Don't use "&function"; functions are like arrays, their address
is their name. Shrink some overlong lines, remove some empties.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Provide helptext which was sometimes missing; update some of it
to be more accurate.
Usage syntax messages have the same EBNF as the User's Guide.
Don't use "&function"; functions are like arrays, their address
is their name. Shrink some overlong lines; remove some empties.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Provide helptext which was sometimes missing; update some of it
to be more accurate (mostly they display something w/no args).
Usage syntax messages have the same EBNF as the User's Guide.
In some cases, *exactly* what the user's guide shows... e.g.
talking about "offset" not "address" for trace_image.
Don't use "&function"; functions are like arrays, their name
is their address.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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If fastdata access fails, then fallback to default mips_m4k_write_memory
Remove unnecessary fastdata loader verify check
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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JTAG has only two possible JTAG ack codes for APACC and DPACC
register reads/writes. Define them, and remove empty "else"
clause in the code which now uses those codes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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I think some of these assumptions are not well-founded.
Related, that swjdp_transaction_endcheck() is a bit iffy.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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reorder the pracc access so we can save a few access cycles
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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remove unnecessary nops when accessing ejtag pracc
general fastdata patch cleanup
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Rename DAP_IR_* as JTAG_DP_* since those symbols are specifically
for JTAG-DP (or SWJ-DP in JTAG mode), and won't work with SWD.
Define the JTAG ABORT and IDCODE instructions for completeness;
add a comment about where to (someday) use ABORT.
Fix messaging which assumes everything is an SWJ-DP; say "JTAG-DP"
instead, it's at least more appropriate for all JTAG transports.
Shrink the affected lines.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Fix: don't print the BASE address except if it's a MEM-AP;
that's an unlikely error, but there's no point getting it wrong.
Tweaks: comments, capitalization.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Make some private functions "static". Remove their public declarations,
and what is now an obviously unused function. Shrinks this object's size
(about 5% on x86_64) while making the code's scope easier to understand.
Shrink the affected lines.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Instead of magic numbers, use their AP_REG_* constants. Rename
the ROM address symbol as BASE to match ARM's documentation.
Comment various other symbols in the header; add some missing ones.
Remove an unused struct. Add some doxygen for stuff including the
DAP structure and initialization.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Shrink some lines, add some comments, simplify some tests.
During debug startup, log the core revision level too.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Most commands are usable only at runtime; so don't bother saying
that, it's noise. Moreover, tokens like EXEC are cryptic. Be
more clear: highlight only the commands which may (also) be used
during the config stage, thus matching the docs more closely.
There are
- Configuration commands (per documentation)
- And also some commands that valid at *any* time.
Update the docs to note that "help" now shows this mode info.
This also highlighted a few mistakes in command configuration,
mostly commands listed as "valid at any time" which shouldn't
have been. This just fixes ones I noted when sanity testing.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Handlers for commands
- arm7_9 semihosting <enable | disable>
- $_TARGETNAME arp_reset assert 1
didn't check if target has already been examined, and could
segfault when using the NULL pointer "arm7_9->eice_cache".
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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The handler for "arm9tdmi vector_catch ..." did not check
if target has already been examined. Without this fix it
segfaults when using NULL pointer "arm7_9->eice_cache".
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Print "ssize_t" as "%ld" (+ cast to long) not as "%zu".
Official MinGW (gcc 3.4.5) doesn't understand "z" flag.
Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Modern versions of GDB can understand VFP3 and iwMMXt hardware.
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Don't forget to list target/arm_opcodes.h
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Misc:
- Introduce some "struct reg" temporaries, for clarity
- Shorten lines
- Add some missing whitespace
- Clean up comments
- Add notes about some fault handling issues
- Most of these errata workarounds are for *OLD* chip revisions
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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And add my copyright. MPCore is untested, but it's the
only other ARM11 core to care about.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Command "reset halt" checks if PC properly resets, issueing warning:
"PC was not 0. Does this target need srst_pulls_trst?".
Checking PC against 0 is not always correct.
Removed PC value check, as suggested by Øyvind Harboe.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: U-PROPRIET-28D9DF\PROPRIETAIRE <PROPRIETAIRE@propriet-28d9df.(none)>
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Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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In conjunction with manual register setup, this lets the ETM trigger
cause entry to debug state. It should make it easier to test and
bugfix the ETM code, by enabling non-trace usage and isolating bugs
specific to thef ETM support. (One current issue being that trace
data collection using the ETB doesn't yet behave.)
For example, many ARM9 cores with an ETM should be able to implement
four more (simple) breakpoints and two more (simple) watchpoints than
the EmbeddedICE supports. Or, they should be able to support complex
breakpoints, incorporating ETM sequencer, counters, and/or subroutine
entry/exit criteria int criteria used to trigger debug entry.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Change handling of the CYCLE_ACCURATE, BRANCH_OUTPUT, and
TRACE_* flags; also the CONTEXTID size values.
- Convert to symbols matching the actual register bits, instead of
some random *other* bits (and then correcting that abuse).
- Get rid of a now-needless enum.
- Keep those values in etm->control, and remove etm->tracemode.
These values all affect the trace data that's recorded by a trace
pod or in the ETB. I modified the file format used to dump ETB
data; since it's fairly clear nobody can use this mechanism now,
this can't cause anyone trouble.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Provide better comments for the ETM_CTRL bits; use the correct bit
for half/full clock mode; and define a few more of the bits available
from the earliest ETM versions.
The new bit defintions use ETM_CTRL_* names to match their register
(instead of ETM_PORT_* or ETMV1_*). For clarity, and better matching
to docs, they are defined with bitshifting not pre-computed masks.
Stop abusing typdefs for ETM_CTRL values; such values are not limited
to the enumerated set of individual bit values.
Rename etm->portmode to etm->control ... and start morphing it into a
single generic shadow of ETM_CTRL. Eventually etm->tracemode should
vanish, so we can just write etm->control to ETM_CTRL.
Restore an "if" that somehow got dropped.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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This command was misplaced; it's not generic to all traceport drivers,
only the ETB supports this kind of configuration. So move it, and
update the relevant documentation.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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We can actually do the right thing if the MMU is off; save
the error message for the phys-but-MMU-enabled path, which
is what isn't yet supported.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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PXA3xx has more than five bits in IR.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Teach ARM11 how to use:
- the new "reset-assert" event
- vector catch to implement "reset halt"
- use SRST more like other cores do
- ... including leaving post-SRST delays up to config scripts
This gives OMAP2420 the ability to reset, and doesn't seem to
cause new iMX31 problems.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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There is no "STMMIDA" instruction. There is however "STMDAMI".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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