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2012-12-23stlink: rename stlink cmd namesSpencer Oliver
As part of the switch to using the hla for the stlink interface we rename the cmds to a more generic name. Update scripts to match new names. Also add handlers for deprecated names. Change-Id: I6f00743da746e3aa13ce06acfdc93c8049545e07 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/921 Tested-by: jenkins
2012-12-23target: add deprecated target name supportSpencer Oliver
This enables us to change the target name without breaking any target scripts. Change-Id: I635f961e573264d3dab2560f3a803ef1986ccfde Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/919 Tested-by: jenkins
2012-12-11mips_m4k: Fixed mips_m4k_resume code for smp targetsKamal Dasu
Fix for bug introduced in in mips smp support code in the resume logic that is checking for wrong return value. Change-Id: Ice3e0069f936b556fecc338ccc12ddba38deeaf6 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1048 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09cortex_a: Fix target entry state route.Evan Hunter
If target is disabled at init, then is examined using 'arp_examine', it can get to cortex_a8_poll with the target state being unknown. Change-Id: Ifffb345bf971d275d2eb1912648b29f0a75f6ccc Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/954 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09mips_m4k: Added SMP debug support for mips architecturesKamal Dasu
This change adds smp debug support for mips platforms. The change leverages the exiting gdb smp support as mentioned in the OpenOCD documentation for using gdb in smp environemnt. Added commands smp_on, smp_off, smp_gdb to control the smp mode. The implementation also provides a way to send Jc packet and toggle the gdb display core context as well. Change-Id: I0835a5aed1844b6ebf8291582912f20695346003 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/937 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09mips_ejtag: Adding EJTAG 4.x and 5.x as valid versionsKamal Dasu
This is a minor change to log EJTAG version 4.x and 5.x as valid versions when debug log is enabled. Change-Id: Ie20458d033c6d22842cb4a31b56765d4ba2ff123 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/936 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-30arm: Mis-aligned data issue fix.Jason Moehlman
Fixes issue with big endian hosts and mis-aligned data on some hosts. Fixes unaligned access exception on hosts that do not support unaligned access when debugging some arm targets. Signed-off-by: Jason Moehlman <jmoehlma@linux-software.com> Change-Id: I6bc6fb1b3c3565b256674b9ef43ed2afd14f5178 Reviewed-on: http://openocd.zylin.com/996 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-11-16mips: patch mips32_pracc_exec_write()Salvador Arroyo
No function writes to MIPS32_PRACC_PARAM_IN addresses and probably has no much sense. Any attempt to write to those addresses should be an error. Change-Id: Iebea5fa9954e2cd56ad34976dd7d25009c6e6388 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/975 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_read_regs() codeSalvador Arroyo
Current code needs 101 pracc accesses for this function, this code needs 12 less. There is a singularity in this code, is the only function that restore a register from param out instead from pracc stack. Obviously the register was previously stored at param out. This save 2 pracc accesses. Change-Id: Ie95b6f983a3198dafc0eab2dd5acc11f871a8d83 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/958 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_write_regs() code.Salvador Arroyo
All the the loads are done with lui and ori instructions, there is no need to save any register, they will be overwritten. Like in the previous patch, for speed optimization in write code, same instructions can be saved if the lower half word or the upper half word is 0. If the lower half word is 0, it can be loaded with only a lui instruction. If the higher half word is 0 it can be done with an ori instruction with register 0. This code saves 10 pracc accesses at a minimum, and 40 at a maximum, obviously if register 2 to 31 are 0 or a half word is 0 Current code needs 91 pracc accesses. Change-Id: I892c5b440191d0c7a474c96845d41c373b7fc637 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/957 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
2012-11-16mips: optimize write code for speedSalvador Arroyo
All the writes are done by the new function mips32_pracc_write_mem_generic(). The code is similar to the read generic code. The reuse of register 15 as memory base address saves 3 pracc accesses. The first write takes 13(12) pracc accesses and for additional writes 3(2). Loading miniprograms should take 25% less time and loading fastdata transfer handler code should be over 2x faster. Change-Id: Ia3b24ba084af33be99da19f00a7fd4d1b291f350 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/956 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize read code for speedSalvador Arroyo
Really nothing new that not explained in previous patches. The code is expanded as needed, there are no loops in pracc code. For the first value pracc accesses are reduced from 39 to 16 and for aditional values from 10 to 3. dump_image should work around 3x faster. Change-Id: I37c9b13395c09eb52a91f10cdb6cbaedef8ab98b Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/955 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_read_u32() functionSalvador Arroyo
This function is highly optimized, there is not much to improve. Loading the base address for pracc access with the new defined MIPS32_PRACC_BASE_ADDR saves one instruction. The memory address is loaded in too steps. First the upper address is loaded. The lower address is passed as an offset in the memory load instruction. The offset is signed, if the lower address is in the range of 0x8000 to 0xffff the offset is a negative value, and the upper address must be incremented by 1. Pracc accesses are now 12 instead of 14. Change-Id: I286945b240ed5c5d5cc540780a41a8a5fa075da3 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/952 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize CP0 read/write codeSalvador Arroyo
MIPS32_PRACC_BASE_ADDR is defined as 0xFF200000. Now is possible to load the base address with a lui instruction and only one pracc access. Offsets to the pracc code addresses are defined to simplify the code and probably make it a bit more readable or self-explained. Change-Id: I853dd2d7fad52745931cc6e6be68c0ae156d897e Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/951 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
2012-11-16mips: code clean up in mips_m4k_debug_entry() functionSalvador Arroyo
The function mips_ejtag_read_debug() is defined in mips_ejtag.c and is called only by mips_m4k_debug_entry() for reading the CP0 debug register. The comment in this function is obviously wrong. There is a generic function to read CP0 registers with similar code. A call to mips32_cp0_read() should work in the same way. The purpose of reading the debug register is to test if the DSS bit is set and clear the SSt bit. It is faster and easier if the SSt bit is cleared without any check. Remark: DSS bit set only means that a debug single-step exception ocurred, but it is not possible to step over a sdbbp instruction, in this case DSS will not be set and the SSt bit not cleared by code. Resume command at another address will step, so really the behavior is not the same. Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/950 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips_ejtag_step_disable() codeSalvador Arroyo
The code is a bit large compared to mips_ejtag_step_enable(). With the mips32 xori instruction the code can be reused. The number of pracc accesses are reduced from 18 to 7. Change-Id: If3974ebd64da4461c22b089796646990e68e1b72 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/944 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-06target: add async algorithm timeoutSpencer Oliver
An issue was observed when using an async algorithm with a target that had not been previously reset beforehand. The target would enter a infinite loop within target_run_flash_async_algorithm. Add a timeout that will at least prevent this issue from happening. and also suggest the user resets the target. Change-Id: I5277e0d64e252d3d353e8d5bc9889a37fdc63060 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/949 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2012-11-06ARM v4/v5 target files: mrc and mcr help information is incorrect.Karl Kurbjun
The order of the mrc/mcr command matches the ARM Architecture Reference Manual. This patch corrects the help information for mrc/mcr. Change-Id: I1f0e6a628a3644124591a6aa291b8a58cfd93b44 Signed-off-by: Karl Kurbjun <kkurbjun@gmail.com> Reviewed-on: http://openocd.zylin.com/914 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-06cortex: autostep correctly handle user breakpointSpencer Oliver
If we halt due to a breakpoint make sure that we do not remove it during a step, only remove breakpoints we have created. Change-Id: I060168e54e53637d4fbf3cbcf62072efdb353807 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/947 Tested-by: jenkins
2012-11-06cortex_m: Fix single stepping will not return to debug mode sometimesPeter Horn
This occurs when stepping past a breakpoint on a even address with maskisr option set to auto With -d3 the following log message appears in this case: "Debug : Interrupt handlers didn't complete within time, leaving target running" Cause : Given a breakpoint is set on the lower half word and the PC is on the upper half word. When another breakpoint is now set on the current PC then resuming the core will not result in a break on the newly set breakpoint. This has been observed on a STM32F1x, STM32F2x (CM3) but not on a STM32F0x (CM0). It's not clear if this is a STM32F1/F2 only or a general CM3 problem. Change-Id: I384813f3bfdf935373b5e23cdb2d7f243c70cc00 Signed-off-by: Peter Horn <peter.horn@bluewin.ch> Reviewed-on: http://openocd.zylin.com/864 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-05cortex_m: fix define formattingSpencer Oliver
Change-Id: Ibdec882b2afc7e16f2361f86715463e030a54964 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/963 Tested-by: jenkins
2012-11-05rtos: Add FPU detection to ChibiOS/RTMatthias Blaicher
The stacking of ChibiOS/RT depends on the usage of an FPU. If the FPU is enabled the FPU registers are also saved on context switch. This patch adds automatic detection of FPU for armv7m targets. Note: With this patch, openocd will only output an error message warning that the FPU is enabled. For further FPU support, the correct stacking information also needs to be added. Change-Id: I0984cbd9180f247ba2fa610e74a6413cc54239ea Signed-off-by: Matthias Blaicher <matthias@blaicher.com> Reviewed-on: http://openocd.zylin.com/961 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-10-31Ensure Cortex-M reset wakes device from sleep (wfi/wfe)Evan Hunter
Change-Id: Idb52ca3123bb3e2f7863ba1b82ac9b176d7cb094 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/833 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-10-28gdb: use strncmp rather than strstrSpencer Oliver
All the packets received will be at start of the packet buffer, so use more efficient strncmp. Change-Id: Ib9c45d8f53425367006b1f880c1bde27f03a6cf9 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/932 Tested-by: jenkins Reviewed-by: Matthias Blaicher <matthias@blaicher.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-28adi_v5_jtag.c: Avoid infinite recursion in jtagdp_transaction_endcheck()Andreas Fritiofson
Change-Id: I81163d9c2ff97ed768f8a3ac1505a8d2b5016b91 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://openocd.zylin.com/908 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2012-10-18stlink: fix vector catch not being clearedSpencer Oliver
Seems after a reset the stlink is not clearing the vector catch (VC_CORERESET) in the Debug Control Register. This has the side effect if the user presses an external reset the core will halt, this patch fixes that. Change-Id: Ic3b2c3991b79cacbbd901c02b79613c2e204e71f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/905 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-10-07Revert "target: remove unused working area 'user' field"Spencer Oliver
This reverts commit 63a23e6fc862b94f00e0833ab474bd02901a019f Change-Id: I62778fb3b1dabc6470d582bea9ca64d593999233 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Change-Id: Iaf5a2cf5bdc4a62ba68ad9403e1c1229112970de Reviewed-on: http://openocd.zylin.com/899 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-09-27Add extra Coresight component ROM identifiers for the Cortex-M4Evan Hunter
Signed-off-by: Evan Hunter <ehunter@broadcom.com> Change-Id: Iaf2d69cf10c341d3a516986677f69a4389b29b1a Reviewed-on: http://openocd.zylin.com/841 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-09-06cortex_m: suggest using hardware srst if VECTRESET usedSpencer Oliver
If the target does not support SYSRESETREQ we fall back to using VECTRESET. This however does not reset the peripherals and we issue a warning to the user to suggest using a reset-init script. Also suggest that using hardware srst will give them the same functionality as using SYSRESETREQ. Change-Id: Ie1781c4b849fed66c52222e6539735537c879fb3 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/802 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-29stlink: fix typoSpencer Oliver
Change-Id: I5fe7b695b00faef966e7621614bbd60b6e694a4f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/800 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-29arm7_9: Fix broken halfword/byte memory readsAndreas Fritiofson
Always scan out all bits, but make sure only the allowed number of bytes end up in the caller-provided buffer. Discard the rest by adding another scan field when size < 4. Rewrite the endianness callback to avoid reading outside allocated memory. Make it directly usable as a callback without the need for a wrapper. Move the shared callback to a more suitable home in arm7_9_common. This fixes the regressions introduced in commits 991ed5a2b657e660f744eefddb084724e52938ea cb90d32e386a7489d31136997209c61e9559ff5e and c3074f377c1da33ca8ba8493826e1b52351eebc6 Change-Id: Ia8bde8c5a9844e89a1d6c0bc8534cd26f02f8d11 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/789 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-24Severe bug in Pracc codeSalvador Arroyo
The function wait_for_pracc_rw() fails if Pracc bit is 0. The variable ejtag_ctrl is loaded with the content of the control register in the first scan. In the second scan Pracc bit is scanned out as 0, letting the proccesor go. The result is unpredictable. All the strange data corruption when scanning at certain frequencies, or the strange delays needed when entering or leaving fasdata area are retated to this bug. Now the code works at any scan frequency, tested up to 15000Khz and indepently of processor speed, tested at 31.25Khz and 4/8Mhz. Change-Id: Iedfd81d06d6af4bc738a521f720e42323025b268 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/769 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-24target: remove unused working area 'user' fieldSpencer Oliver
working_area::user has never been used so lets remove it. Change-Id: I1200311b34248549c1fe30c9f675e6129b7bebee Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/781 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-24build: fix clang warningsMartin Nowak
Change-Id: I3c6a63a18034535f0a8c2c62ba8a708f09d7839b Signed-off-by: Martin Nowak <dawg@dawgfoto.de> Reviewed-on: http://openocd.zylin.com/765 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-24target: catch dap_lookup read errorSpencer Oliver
Issue found by clang-3.1 Change-Id: I2e922ec83117e75db5bec1e82edaa75a9e6e7464 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/778 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-02target: add valid smp target checkSpencer Oliver
Check that the target is valid before calling any target functions. Change-Id: I538fccc79d5ec89976e14beab02cb20490b299bb Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/766 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-01arm946e: add icache/dcache manipulation commands.Alexander Osipenko
Provide cache operations coherent with internal target state. Functions similar to xscale target. Change-Id: Ic6b9a894154f6e4f5672b5d7f5035c9774ee9499 Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/695 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-01arm946e: cp15 command returns value to the scriptAlexander Osipenko
Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-01arm946e: cleanup C0.C cache type reg accessAlexander Osipenko
Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-08-01arm946e: don't use global variables for contextAlexander Osipenko
Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30Bugfixes in mips32_pracc.cSalvador Arroyo
When testing a pic32mx220f032b with different values for adapter_khz and cpu clocks i was getting a lot of corrupted data from the chip. From time to time openocd fails with segmentation faults or is aborted due to memory corruption. Change-Id: I134743f75c477b3d55dc74ae4474598e153b4a4a Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/690 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30Speed up mips_m4k_write_memory()Salvador
Do not call mips32_cp0_read() if not needed. This will speed up execution of mips_m4k_write_memory() by near 2x, with parameter count = 1. Change-Id: I7829a7802b6475bc6d4ac3f0632d8d239d1072da Signed-off-by: Salvador <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/624 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-11target: Cortex-M use consistent arm dap accessSpencer Oliver
Purely cosmetic but use the same style as Cortex-A target, this makes searching refs easier. Change-Id: I732ad9701f561e2312c5d191f5aaffd3a2f2393d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/731 Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2012-07-11stlink: fix arm semihosting supportSpencer Oliver
Add missing arm cmd handlers that enable semi hosting support to work as expected. Change-Id: I063d82c48b82b4f6aed4efc4b08ea752d78e9047 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/734 Tested-by: jenkins Reviewed-by: Alan Bowman <alan.michael.bowman@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2012-07-11target: detect correct Cortex-M tar auto increment sizeSpencer Oliver
The ADIv5 spec guarentees that tar_autoincr_block will be 10bits. Make this the default for Cortex-M family until we detect a Cortex-M3/M4, we then change autoincrement to 12bits. Change-Id: Ie8c89134aa036879bdd8a3c312cee9715dbc6913 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/730 Tested-by: jenkins Reviewed-by: simon qian <simonqian.openocd@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-11target.c, jim_target_md using command_print_samelineVandra Akos
jim_target_md is supposed to print out results with command_print in hexdump format. It was using command_print which appends a newline character aftre every invocation. Using command_print_sameline instead Change-Id: Iaff03021acc38d54b5a082cb58b82aa4449c0715 Signed-off-by: Vandra Akos <axos88@gmail.com> Reviewed-on: http://openocd.zylin.com/669 Tested-by: jenkins Reviewed-by: Alexander Osipenko <sipych@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-11target/target.c, jim_target_md refractoredVandra Akos
- Added a few lines of comment before the function explaining the usage and the output generated by the command - Added a few lines of comment in the body explaining what is happening to improve code readability - Renamed a few variables to improve readability: * a -> addr * b -> dwidth * c -> count - Added a new variable, named byte to contain the number of bytes to read, instead of overwriting the count parameter, to avoid confusion between the two values. Change-Id: I5828ec0f5aadaa39becec7b84f198756bb2c3d41 Signed-off-by: Vandra Akos <axos88@gmail.com> Reviewed-on: http://openocd.zylin.com/665 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-05-28build: remove src file execute permissionSpencer Oliver
Change-Id: I42a250cdfcd03424a63cd1a255f9cf4a3c6e3ccd Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/671 Reviewed-by: Xiaofan <xiaofanc@gmail.com>
2012-05-25target: fix segfault in arm7_9 8/16bit readSpencer Oliver
Seems I5347352e7595686634bd0de13fcf6de6e55027b0 introduced an issue when reading 8/16 bit data - the in buffer was always set to 32bits. Change-Id: Ife2bb6a20fcb3ec0e486655512164f25ae9196b4 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/660 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de>
2012-05-22stlink: check read_reg resultSpencer Oliver
Change-Id: I284824aa6f5eae8f6e910a482e9f7435e649fc0d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/657 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: jenkins
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-18 01:21:18 +0000