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2013-07-01armv4_5: prevent segfault when gdb connects to an underinitialised targetPaul Fertser
This prevents segmentation fault that can occur on cortex_a targets if gdb connection is established before it's halted and CPSR examined. Change-Id: Id996200e0fd95440496509c1fecaabbdbf425e23 Tested-by: Henrik Nordstrom <hno@squid-cache.org> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1446 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-07-01cortex_m: deprecate soft_reset_haltSpencer Oliver
soft_reset_halt was only really intended for the older arm arch, eg. armv4/5. Newer arch such as armv7m/mips do not need this as they have better alternatives. Change-Id: Ifb360680b7e4bfa5365f3c79d82574bded952b45 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1442 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-14hla: Add Simulated DCC register for target communicatonBrent Roman
Change-Id: I193be169059caba661e46de8081d7e92f92cafee Signed-off-by: Brent Roman <brent@mbari.org> Reviewed-on: http://openocd.zylin.com/1364 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-12[RFC] mips: Enable bulk write optimization for all writesAndreas Fritiofson
mips_m4k_bulk_write_memory was only called from target_write_buffer as an optimization when the word count was large enough. Remove mips_m4k_bulk_write_memory from the target type, causing the default implementation to call the regular mips_m4k_write_memory instead. Perform the dispatch to bulk write in mips_m4k_write_memory, enabling the optimization for target_write_memory() writes with size 4, in addition to target_write_buffer() writes. It also enables making the choice of bulk write vs regular write specifically for the architecture and not relying on the generic target code to make a sensible decision. Change-Id: I295f21a67ceaa195802403f2518ea2e0a025c1c7 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1215 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
2013-06-12cortex_a: remove memory leak on failureSpencer Oliver
If mem_ap_sel_write_atomic_u32 fails then tmp_buff may not be released. Detected by clang. Change-Id: I3d5416bd47d0eea61f61ec02ac5e43c82f114108 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1433 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-12Change variable scope.Jim Norris
Change scope of the variable gdb_reg_list_idx from global to module. Change-Id: Ib8273c0769c11c1d5a338e4711efbddb8e8a0243 Signed-off-by: Jim Norris <u17263@att.net> Reviewed-on: http://openocd.zylin.com/1441 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-06-05nds32: add new target type nds32_v2, nds32_v3, nds32_v3mHsiangkai Wang
Add target code for Andes targets. Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1259 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-05aice: add Andes AICE supportHsiangkai Wang
Andes AICE uses USB to transfer packets between OpenOCD and AICE. It uses high-level USB commands to control targets instead of using JTAG signals. I define an interface as aice_port_api_s. It contains all basic operations needed by target-dependent code. Change-Id: I117bc4f938fab2732e44c509ea68b30172d6fdb9 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1256 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-03cortex_m: print 'Cortex-M' rather than 'Cortex-M3'Spencer Oliver
This file is used by all the Cortex-M family not just Cortex-M3. Change-Id: Ie8680535b220c66bb8fcd862510407a46a73e8a0 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1429 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-03cortex_a: fix FTBS on ARM due to alignment issuesAndreas Fritiofson
Native compilation on RaspberryPi with gcc (Debian 4.6.3-1) 4.6.3 Target: arm-linux-gnueabi ends with error: cortex_a.c: In function 'cortex_a8_read_apb_ab_memory': cortex_a.c:2063:40: error: cast increases required alignment of target type [-Werror=cast-align] cc1: all warnings being treated as errors Also check for malloc failure. This patch is compile-tested only. Change-Id: I580c505424d03ac3a565de54182db22277c52ac1 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1369 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-05-29cortex_m, hla_target: do not try asserting SRST if it's not presentPaul Fertser
This should cover all the cases when RESET_SRST_NO_GATING is set without RESET_HAS_SRST. This might happen when RESET_SRST_NO_GATING is automatically set by a target code (and not from tcl). However, there're some other places (mips_m4k, arm7_9_common) where adding RESET_SRST_PULLS_TRST would lead to trying to use SRST even if it's not present. Currently it's impossible for the user to enable that flag without enabling SRST. Change-Id: Ib1c6f68feed0b8057d55afd5f260bb22ab332ced Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1405 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-05-28targets: fix target_type name for Cortex-A targetsPaul Fertser
Commit d9ba56c295f057e716519a798bf9cdb4898c24f4 did a bunch of renaming of cortex_a8 to cortex_a, including the names in config files. However that introduced a regression as the name in target_type struct remained unchanged. This adds the last missing bit: actual renaming of the target name as understood by OpenOCD. Also change the (hopefully) last instance of using it in the supplied config files, namely from imx6.cfg. Change-Id: Ib9289fc6d946630133ec6e36c20015ccb50acf61 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1420 Tested-by: jenkins Reviewed-by: Chris Johns <chrisj@rtems.org> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-05-10Added functionality to the SYS_SYSTEM semihosting call.Brandon Warhurst
There seems to be a few missing semihosting calls. I am not sure why this one is actually missing, since it seems simple enough to implement. It was tested using an HTC HD7 connected to openocd through a "home brew" ftdi 4232H board. Change-Id: Ie17dc96c6d48227a3dc9ff1e21201a85498a10b1 Signed-off-by: Brandon Warhurst <roboknight@gmail.com> Reviewed-on: http://openocd.zylin.com/1345 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-28target: rename cortex_a8 to cortex_aSpencer Oliver
Rename cortex_a8 target to use a more correct cortex_a name. This also adds a deprecated_name var so that older scripts issue a warning to update the target name. cfg files have also been updated to the new target name. Change-Id: I0eb1429c9281321efeb444b27a662a941a2ab67f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1130 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-28target: rename cortex_m3 to cortex_mSpencer Oliver
Rename cortex_m3 target to use a more correct cortex_m name. This also adds a deprecated_name var so that older scripts issue a warning to update the target name. cfg files have also been updated to the new target name. Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1129 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-28cortex_m: remove old target breakpoints/watchpointsSpencer Oliver
Sometimes the target may have breakpoint registers set from a previous debug session, we can either sync them or as we have chosen here clear them. Change-Id: I439a623ebbf010246a70e5596d04aa7d546da731 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1363 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-28arm: fix arm reg regressionSpencer Oliver
Seems commit fc2abe63fd3cea7497da7be2955d333bd3f800b9 caused a regression in that the arm reg cmd no longer worked. The issue was caused because we changed the value of ARM_MODE_THREAD which was being checked in arm_init_arch_info. Change-Id: Id571d4ab336d1b0e2b93363147af245d24b65ca5 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1362 Tested-by: jenkins Reviewed-by: Luca Bruno <lucab@debian.org> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 4Salvador Arroyo
Now all the functions with only fetch accesses are modified. The same delay between scans has been added to mips32_pracc_fastdata_xfer(), it should work at the same scan rates as the other pracc functions, but it needs higher scan_delays to work. Change-Id: Ifb31d8ea6de9d22674385782913d221a2494dbbf Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1196 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 3Salvador Arroyo
Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified. mips32_cp0_read() is very similar to mips32_read_u32() with one store access. mips32_pracc_read_regs() is the only function that can not be executed from only one queue. Now this function is modified to use reg8, it saves all the registers but does not restore reg8. To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and restore it from ejtag info instead of using DeSave for save/restore. Change-Id: Icc224f6d7e41abdec94199483401cb512cc0b450 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1195 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 2Salvador Arroyo
Each pracc function defines a variable ctx of type struct pracc_queue_info. To simplify the code tree auxiliary functions are defined: pracc_queue_init(), pracc_add() and pracc_queue_free(). The second parameter in pracc_add() is the store address if the instruction is a store at dmseg, otherwise it should be 0. The code is executed by mips32_pracc_queue_exec(). If ejtag_info->mode is 0 mips32_pracc_exec() is called and it should work like with current code. To generate the delay between scans the number of clock ticks are calculated with the help of jtag_get_speed_khz(). Due to delays in the execution of each single ftdi instruction the number of ticks are higher as it should be, specially at higher scan rates. mips32_pracc_read_u32() should now work with the new code. Change-Id: I471590a4fc89b56af10bd46c48767b4c64de154f Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1194 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 1Salvador Arroyo
This patch and the following patches define another way of doing processor access without the need to read back the pracc address as needed in current pracc code. Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200 and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start. Most of the processor accesses are fetch and some are store accesses. After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses. The pracc address for a store depends only on the store instruction given before. m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline. For reference: MD00249 mips32 m4k manual. A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by current code or by the new one to generate the sequence of pracc accesses. For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96(). This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution. The pracc bit is not checked before execution, is checked after the queue has been executed. Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay between scans is added by calling jtag_add_cloks(). A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it. A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set, current code is executed, if lower, new code is executed. Initial default values are set in function mips32_init_arch_info. A reset does not change this settings. Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1193 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-11arm_adi_v5: fix for csw nonsecure access.Michel JAOUEN
Add command to fix CSW_SPROT in register AP_CSW. This solves dap apmem access in non secure access. Change-Id: I7cfcb6434d75f5cfd4a2630a059901cdeea010ce Signed-off-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-on: http://openocd.zylin.com/1276 Tested-by: jenkins Reviewed-by: mike brown Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02mips: code cleanup in cp0 command handlersSalvador Arroyo
After calling mips32_cp0_read() nothing has been queued, the call to jtag_exec_queue() is unnecessary. Change-Id: Ie25438045a8e9b6b1b170df7b52609d45f284b5a Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1190 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02mips: change in restoring debug working registerSalvador Arroyo
In current devel code there are 3 functions (related to m4k code) that need to restore register 8 from pracc stack: mips32_pracc_read_u32() mips32_cp0_read() mips32_pracc_write_mem_generic() And mips32_pracc_read_mem() needs to restore regs 8 and 9 from pracc stack. Values in this registers should be the same as read by mips32_pracc_read_regs() when entering debug mode and can be modified by mips32_pracc_write_regs() when leaving debug mode. There is no need to read their values from the processor registers every time. The fields reg8 and reg9 are added to struct mips_ejtag to store these register values and the call to mips32_save_context() is shifted in mips_m4k_debug_entry() in order to store them before any other function needs to restore these registers. For the same reason in function mips_m4k_step() the call to mips_m4k_set_breakpoint(), if needed, should be made after calling mips_m4k_debug_entry(). For single word write the number of pracc accesses are now 9 or 8, from 13 or 12 in current code, single word read takes now 10 instead of 12. This patch is really the first in a set of patches for an alternate m4k pracc code much faster that current code. At least for me with pic32mx works fine. Change-Id: Ibd9df5e8b9f78ce05a180949ba6a561c761b61d6 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1146 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02mips: mips32_pracc_fastdata_xfer() little modificationSalvador Arroyo
In this function after loading the handler code and the jump code there is a call to wait_for_pracc_rw() to verify that a pracc access is pending. Next the address is read to verify that the handler is running, the address should be at fastdata area. Next, another call is made to wait_for_pracc_rw(). This call is not needed, we now already that a pracc access is pending. Better we call this function before loading the end address to be sure it is loaded correctly. Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Change-Id: If311450ea634786fc28cf1a8e18ed24ce5257d20 Reviewed-on: http://openocd.zylin.com/1142 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02pic32mx: false pending at low core clockSalvador Arroyo
To show up the fail try to step with the core clock set to 31.25Khz and with a ftdi/hs adapter or with a wiggler, -not with ft2232-. The scan frequency should be set to 300Khz or higher, at lower frequency probably will not fail. The code exits with error because the pracc address is at 0x0. It also fails when using the "all" register, but in this case the code works without any message because the pracc address is at 0xff202004 when it fails. I never saw this fail with the core clock set to 500Khz or higher, but ... The workaround simply puts a 1 ms delay after the execution of the DERET instruction. Change-Id: I38e8c01a9c39aedd3282140543b83a0844d8ad29 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1139 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02Add abort when JTAG-DP transaction times out.Evan Hunter
Fixes system hang for devices that don't ignore transactions to bad addresses. Change-Id: Ia98344d7efc12951ef79dbc82b8f792b70a22cee Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/1115 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02arm_adi_v5: fix mem_ap_read_buf_u32() JTAG nastiness..mike brown
Moved JTAG code out of transport-neutral file (arm_adi_v5.c) into transport specific file (adi_v5_jtag.c). Added ap_block_read to dap_ops interface (arm_adi_v5.h) to support the move. Change-Id: I796d3984f138aad052b97c77ac9c12ffd1158f74 Signed-off-by: mike brown <mike@theshedworks.org.uk> Reviewed-on: http://openocd.zylin.com/1277 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15target: fix broken Cortex-R4 supportSpencer Oliver
This regression was caused due to the recent addition of R4 support and the removal of the bulk_write_memory handler. Change-Id: Ide692737f235c0e9906becb6f3502ba52c5907aa Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1246 Tested-by: jenkins
2013-03-15target: Retire target_bulk_write_memory()Andreas Fritiofson
The only caller was arm_nandwrite(). Replace that call with target_write_buffer() instead, which in turn may end up calling the same bulk_write_memory target API function. Change-Id: If34c7474df5cf14af3b732fb4774816818f28e79 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1214 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15target: Add default implementation of bulk_write_memoryAndreas Fritiofson
Remove dummy implementations from all targets except arm7_9 and mips, which are the only ones with real implementations. Replace with a single default implementation simply calling target_write_memory(). Change-Id: I9228104240bc0b50661be20bc7909713ccda2164 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1213 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15arch: Added ARMv7R and Cortex-R4 supportEvan Hunter
Rewrite to merge Cortex-A and Cortex-R code Change-Id: I4541557980d43d1bba6e8d1bfeb04f536ed25a00 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/358 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15adi_v5: search for Debug and Memory AP supportEvan Hunter
Adds dap_find_ap() function. Change-Id: I6643025624009b12d4936de67a605da52c07be49 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/909 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15cortex_a : optimize apb read/write access.Evan Hunter
Rewrite: Adheres more closely to 'fast read/write' examples in TRM. up to 50x faster Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/903 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove read_memory_impAndreas Fritiofson
Change-Id: Idc6ef3b075ccbb5945df8fea746011cb17175d8f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1219 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove write_memory_impAndreas Fritiofson
Change-Id: I5d933bc19443bba8a0193c90471fdd0614324a92 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1218 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove soft_reset_halt_impAndreas Fritiofson
Change-Id: I12c907584ef73de570eba2dcfeb8477cabc6098f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1217 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-06target: use common target_name to access target::cmd_name memberSpencer Oliver
Change-Id: I203b89ef25a072c3b00b504483d5f2a83477fad6 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1182 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-03-05Move back off timer to target structMathias K
Move the global target back off timer to the target struct. This will fix the wrong error handling with multi target devices like smp systems. Change-Id: Ia327182ed5d13ca87323700017a8c40ecc6b25a3 Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/1179 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-03-05Add the target name to debug output for better understanding and error ↵Mathias K
identification. Change-Id: I1054debea6cd3a6548aadeae2d84000a0039814e Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/1178 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-02-26gdbserver: use common hexify/unhexify routinesSpencer Oliver
Change-Id: I9989b625666e9c60ec9867cf6f4d94f41c998c3f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1105 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2013-02-25target: hla correctly use target eventsSpencer Oliver
Because we were always running using target state TARGET_RUNNING target algorithm's were a bit verbose compared to other targets. This brings the hla target inline with the other targets. Change-Id: I3a257fdc878b87660fac8b5eca22b421eee5b349 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1134 Tested-by: jenkins
2013-02-25armv7m: update to use correct register core_cacheSpencer Oliver
The was missed when the armv7m was moved over to using the std arm core_cache, probably because it is disabled by default. Change-Id: I2f5a18ef6dd783b36e8c29f4c52379104bda4583 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1138 Tested-by: jenkins
2013-02-02armv7m: use ARM_MODE_THREAD core mode for algoorithm'sSpencer Oliver
This makes sure we are using privileged mode when executing any loaders. Change-Id: I18bf32ec92e1c76a66ab25e3712652bc3650b332 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1108 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: restore core mode after executing algorithmSpencer Oliver
Make sure we restore the core mode after executing any algorithm. We also now check that we actually need to swap the core mode, we may already be in the correct mode. Change-Id: Ia48af2c108e0f9868aae241bf25f60323503f092 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1107 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic arm read/write_core_regSpencer Oliver
Change-Id: I0c15acc1278d2972269d294078495e6b069c830b Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/969 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic register core_cacheSpencer Oliver
This removes the armv7m::core_cache and uses the generic arm::core_cache. Change-Id: If854281b31486cea8be005008f6a71a691b4c208 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/968 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: remove unused armv7m_regtypeSpencer Oliver
This simplifies the armv7m_core_reg structure ready for the move to using the generic struct arm_reg. Change-Id: I8edb9d77cc54965d49cd2e754568ebcea4cf6964 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/967 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic arm::core_modeSpencer Oliver
To simplify things change over to using the generic core_mode struct rather than maintaining a armv7m specific one. Change-Id: Ibf32b785d896fef4f33307fabe0d8eb266f7086f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/966 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-17 19:23:43 +0000