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2018-03-30arm_cti: add cti command groupMatthias Welwarsky
Extend the CTI abstraction to be accessible from TCL and change the 'target' command to accept a cti 'object' instead of a base address. This also allows accessing CTI instances that are not related to a configured target. Change-Id: Iac9ed0edca6f1be00fe93783a35c26077f6bc80a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4031 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-27aarch64: add cpsr bitfields to target descriptionMatthias Welwarsky
provide meta information for the cpsr so gdb can display the status flags and not only a hexadecimal number Change-Id: I9d3fb29153780adbea389d7e4175d5e19bddc256 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4460 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-27tdesc: bitfields may carry a typeMatthias Welwarsky
a bitfield may carry a type (bool or int), add support for that. Change-Id: Ic831a9b8eac8579e8fdd7d0f01b7f1c9259e6739 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4459 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-20transport: add transport_is_hla()Tomas Vanek
and move declaration of all transport_is_xxx() functions to transport.h Change-Id: Ib229115b5017507b49655bc43b517ab6fb32f7a6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4469 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-16aarch64: fix debug entry from EL0Matthias Welwarsky
If we enter debug state from EL0, some registers are not accessible. Temporarily move to EL1H and back to gain access. Also, fix armv8_dpm_modeswitch() to not immediately restore the previous state on elevating the privilege level. Change-Id: Ic2a92109230ff4eb6834c00ef544397a5b7ad56a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4461 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-15target/target: free what leaked in target_destroy()Tomas Vanek
Free event_action, fileio_info and working area. Change-Id: Iac81230423e92304b8e2c971d0ec71a96b693fc4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4412 Tested-by: jenkins
2018-03-15server: free strduped port numbersTomas Vanek
Although the leak is negligible, the clean heap on exit will ease valgrind testing. Change-Id: I3a7a9c8e8dc7557aa51d0b9caa244537e5e7007d Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4410 Tested-by: jenkins
2018-03-13target: hla: check return value of hl_dcc_readPaul Fertser
This should fix "Assigned value is garbage or undefined" warning reported by clang: http://build.openocd.org/job/openocd-clang/doclinks/1/report-391318.html Change-Id: Ib9488fadca871814328501e415f88822291e0c96 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4332 Tested-by: jenkins
2018-03-13target: arm: disassembler: fix Thumb2 BLX decoding addressPaul Fertser
Since BLX in Thumb2 always switches mode to ARM, the PC needs to be 4-bytes aligned. Change-Id: I4f4c194fe21093cecfd9872e1d30588f4adc7257 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4382 Reviewed-by: Philipp Guehring <pg@futureware.at> Tested-by: jenkins Reviewed-by: Paul Sokolovsky <pfalcon@users.sourceforge.net>
2018-03-11armv7a: cache ttbcr and ttb0/1 on debug state entryMatthias Welwarsky
Instead of re-reading ttbcr and ttb0/1 whenever a virt2phys translation is done, cache the values once when entering debug state. Use the cached values in armv7a_mmu_translate_va(). Change-Id: I1bc5349ad2f19b2dd75bdd48468a2c1f1e028699 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3112 Tested-by: jenkins
2018-03-10Support for Arm VFP v3 registers read/writeOmair Javaid
This patch adds support in openOCD to read/write Arm vector/floating point registers. This is compatible with Arm vfp v3 target xml in GDB. Please refer to binutils-gdb/gdb/features/arm/arm-vfpv3.xml Change-Id: Id4dd1bddef51c558f1a86300c1a876d159463f18 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4421 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2018-03-10Support for AArch32 SIMD/Floating-point registersOmair Javaid
This patch adds support for read/write of SIMD and floating-point register in AArch32 mode. This patch is tested using Raspberry Pi3 halted in AArch32 mode with FP/SIMD enabled. Software need to make sure floating-point and SIMD unit is enabled. Change-Id: I2b3b8af02257c6420e5a70c6f4c91f839c1f5ee5 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4446 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-10Support AArch64 SIMD/FP registers read/writeOmair Javaid
This patch adds support in openOCD to read/write AArch64 SIMD/FP registers. This patch depends on a previous patch which adds support to generation of target xml by openOCD with nested architecture defined types. AArch64 SIMD/FP registers assumes various types and to support all types we implement them as architecture defined type aarch64v which in turn consists of various architecture defined types. This is compatible with AArch64-FPU target xml in GDB. Please refer to binutils-gdb/gdb/features/aarch64-fpu.xml Change-Id: I7ffb0c21b3c2e08f13720b765408b30aab2a9808 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4373 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-09Cortex-R : Remove commands which are not relevant to Cortex-REvan Hunter
Change-Id: I8dec85150386c149ffdb7bf4e7e533f16bb63b84 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2877 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-03target: use correct target in target-prefixed commands and event handlersTomas Vanek
This change contains an alternative to Matthias Welwarsky's #4130 (target-prefixed commands) and to #4293 (event handlers). get_current_target() must retrieve the target associated to the current command. If no target associated, the current target of the command context is used as a fallback. Many Tcl event handlers work with the current target as if it were the target issuing the event. current_target in command_context is a number and has to be converted to a pointer in every get_current_target() call. The solution: - Replace current_target in command_context by a target pointer - Add another target pointer current_target_override - get_current_target() returns current_target_override if set, otherwise current_target - Save, set and restore current_target_override to the current prefix in run_command() - Save, set and restore current_target_override to the event invoking target in target_handle_event() While on it use calloc when allocating a new command_context. Change-Id: I9a82102e94dcac063743834a1d28da861b2e74ea Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Suggested-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4295 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-27gdb_server: run control fixes for vContTomas Vanek
this patch contains several changes to run control and state handling together with gdb: - graceful handling of target/gdb desync on resume, step and halt - a default gdb-attach event executing the "halt" command, to meet gdb expectation of target state when it attaches - call target_poll() after Ctrl-C command from gdb - call target_poll() after resume and step through a vCont packet - fix log message forwarding on vCont stepping, also move an aarch64 log message from INFO to DEBUG level to prevent messing up the gdb console during source-line stepping - fix oversight in vCont support that messes up breakpoint handling during stepping Change-Id: Ic79db7c2b798a35283ff752e9b12475486a1f31a Fixes: d301d8b42f0bfe67d76d6f340db6570cc71c876e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4432 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-27Fix incorrect commentChristopher Head
target_start_algorithm does not download the algorithm. It only starts it. It expects someone else to have already written the algorithm code into the proper location before calling it. Change-Id: I5e04406eed0ebb1c23e550dbf8d9f1204c432603 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4435 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-24Expand target_run_flash_async_algorithm() doc comment.Girts Folkmanis
Change-Id: I5d1e8401cbcf0e116a233a2839a06d2c9dbc85ce Signed-off-by: Girts Folkmanis <opensource@girts.me> Reviewed-on: http://openocd.zylin.com/4127 Tested-by: jenkins Reviewed-by: Christopher Head <headch@gmail.com> Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-24stm8: fix compilation warningAke Rehnman
Change-Id: Iedad040384316356442ec87769855fa2960893c5 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/4377 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-02-21target: fix target.working_area typePeter Mamonov
Change-Id: I15cfbe6984656fb0b48d2af5a7e1afa10d47b6ab Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-on: http://openocd.zylin.com/3977 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-21cortex_a: fix handling of Thumb-2 32bit breakpointsMatthias Welwarsky
When debugging Thumb-2 code, Gdb will at times send a breakpoint packet 'Z0,<addr>,3', the number 3 denoting that the instruction to break on is 32 bits long. Handle this by replacing it with two consecutive 16bit Thumb BKPTs and make sure to save and restore the full, original 32bit instruction. Note that this fix is only applicable if you debug a bare-metal program (like the linux kernel) with the 'wrong' gdb, e.g. use an "arm-linux" gdb instead of an "arm-eabi" gdb. But since most people may not know about the subtle differences between gdb configurations regarding thumb2 breakpoints it's still valid. Change-Id: Ib93025faf35b11f0dba747a8c1fc36fd09a4c0f8 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4241 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2018-02-21armv7a: forward error value in armv7a_cache_auto_flush_all_dataOleksij Rempel
if armv7a_l1_d_cache_clean_inval_all will fail, error value is never forwarded. So make sure we do it from now. Change-Id: I02acfaa938ec09f58df77191d13d8f4bb3308720 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4384 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-14Handle improperly build image files gracefullyAndreas Bolsch
Images build improperly (by simply concatenating separate images) were accepted, but anything after the first end-of-file record *silently* ignored. Now emit warning for intel and motorola images upon non-whitespace after first end-of-file record but continue reading anyway. ST ships some images broken that way in their CubeMX packages ... Change-Id: I0c5d08fa90070fed11fb805c5f0dc39817048176 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4281 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-07cortex_a: faster debug initMatthias Welwarsky
Don't use atomic dap operations when not necessary Change-Id: Idc6dcd2bda95f7994852df4ae2a588976f4c9010 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4142 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-30x86_32_common: fix some warningsPaul Fertser
Mostly "Dead assignment" reported by Clang static analyzer. Change-Id: Ibf81d2ba2462570ee3a40e57a60c55a1d1fa0c00 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4351 Tested-by: jenkins
2018-01-29arm_adi_v5: fix return value of mem_ap_read/write for size 0Tomas Vanek
Unhandled marginal case produced a warning in Clang static analyzer. Change-Id: I3e2fc4182fa4f863acfb972b1e7a512fce5bf33a Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Suggested-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/4357 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-29aarch64: clean up scan-build errorsMatthias Welwarsky
scan-build reported a couple of problems with code in aarch64.c, this patch cleans them up. No functional changes. Change-Id: Ie210237ddc840a8bbcd535f86a3a5faf473132f2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4346 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-26aarch64: implement mmu on/off for aarch32Matthias Welwarsky
add decoding of aarch32 core modes (register layout is compatible) Change-Id: I34c3146a7b1f836d3006be2b76b036da055b3d3e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4374 Tested-by: jenkins Reviewed-by: Forest Crossman <cyrozap@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-25Use timeval helpersChristopher Head
Some of these changes actually fix broken comparisons which could occasionally fail. Others just clean up the code and make it more clear. Change-Id: I6c398bdc45fa0d2716f48a74822457d1351f81a5 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4380 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-25target, arm_adi_v5: catch two allocation errorsTomas Vanek
Command mdw 0 0x40000000 triggers Segmentation fault on an arm. Size parameter is a nonsence that may happen e.g. if you mistype mdw instead of mww. Add checking for calloc() NULL return in mdb/h/w. Use calloc() instead of malloc() as multiplication count * sizeof(uint32_t) overflows for size >= 0x40000000. Change-Id: I968c944d863d1173ef932a7077d526fccb9381ae Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4349 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-16aarch64: speed up first examinationMatthias Welwarsky
Don't use atomic dap operations when not necessary. Also remove loop trying to set core power request, didn't find a platform where it actually worked and it's slowing examination down. Change-Id: I44e5c2f289f951b8f4579f08a841172404a52053 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4143 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-16aarch64: simplify mode and state handlingMatthias Welwarsky
Aarch32 and Aarch64 modes don't conflict in CPSR, no need to deconflict ARMv7-M profile modes either. Change-Id: I4c437dfa657f9e8a1da3687bc9f21435384b7881 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4144 Tested-by: jenkins Reviewed-by: Yao Qi <qiyaoltc@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-16aarch64: add 'maskisr' commandMatthias Welwarsky
Allow to configure ISR masking during single-step and add handling for stepping over WFI with ISR masked. Change-Id: I7918be7bcda6a1d9badac44fc36c59b52f662fef Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4023 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-14arm_adi_v5: added some partnumbers found in tegra 186 and tegra 210Jiri Kastner
Change-Id: Icd4137f3e266364d9728672bd2359fbd9a6c8ce9 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/4160 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-13ejtag: added missing instructions.Jiri Kastner
added missing instructions from latest available ejtag specification (MD00047 v6.1 at time of writting) for trace control, fast data channel and pcsample. Change-Id: I30293951611265ffc2bd896f9d3ca6b310e5cac6 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/3950 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13profiling: write "correct" sample rate to gmon outputKarl Palsson
This duration vs sample count is _significantly_ closer to the truth than simply declaring the value to be 100Hz. Change-Id: Ie8d8bdf1959e1aa7cead0631cd2c86afe77d1efc Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/4221 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13hla_target: allow non-intrusive profiling on cortex-mKarl Palsson
Leverages the existing work that added profiling via DWT_PCSR. hla_target doesn't have direct access to the mem_ap for doing a bulk repeated read, but simply reading the DWT_PCSR register repeatedly is still ~2 order of magnitude faster than halt/resume. Change-Id: Ibe451aa95143694398370fdad6939cfb6191d56f Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/4220 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13cortex_m: add profiling functionSimon Schubert
Use DWT_PCSR if present (reads nonzero); otherwise do halt-and-sample pc. Signed-off-by: Simon Schubert <2@0x2c.org> Change-Id: Id2dc4665e5008cc497a2e6e6493522d038d5af42 Reviewed-on: http://openocd.zylin.com/4211 Tested-by: jenkins Reviewed-by: Karl Palsson <karlp@tweak.net.au> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13target: lakemon: implement assert_reset and deassert_resetFelipe Balbi
We're using an I/O port reset by default. The only board currently supported (Galileo) doesn't have SRST routed on the JTAG connector. When using 'reset halt', we must rely on Reset Break because our adapters don't have support for PREQ#/PRDY# signals. Tested with Intel Galileo GEN2. Change-Id: Ia406e31c156f8001717d5b6a08bd03f71de790d3 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Reviewed-on: http://openocd.zylin.com/4016 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13target: quark_x10xx: miscellaneous cleanupsFelipe Balbi
Just some misc cleanups without any functional changes. It's just easier to read. Change-Id: I66bee31f297bcbdb8cc4446b774d7714fbaa7c83 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Reviewed-on: http://openocd.zylin.com/4015 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13target: type: fix indentationFelipe Balbi
No functional changes, cleanup only Change-Id: I53c422be16d0a4ff157745d31362f6483093e5eb Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Reviewed-on: http://openocd.zylin.com/4014 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13target: lakemon: probemode entry isn't instantaneousFelipe Balbi
When testing with Intel Galileo GEN2 I have noticed a few iterations where probemode entry took a little longer. At most I had to read tapstatus twice. This patch uses a loop of up to 100 iterations to wait for tapstatus to update with PM entry results. Change-Id: I1c87d7dde715255b3fd2460d299b9493218533fc Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Reviewed-on: http://openocd.zylin.com/4013 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13target: quark_x10xx: adding missing 'static' keywordFelipe Balbi
These symbols are only used within this C source file. They don't need to be exposed to the outside. Change-Id: Idb04550ecca7f12c3fdc8c6447eeeb871961add3 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Reviewed-on: http://openocd.zylin.com/4012 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13target: arm: disassembler: decode v6T2 ARM MOV{W,T} instructionsPaul Fertser
Change-Id: I32cf2669b1b22d4142f30674cf918e36561a885e Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3899 Tested-by: jenkins
2018-01-13target: arm: disassembler: decode v6T2 ARM ISB instructionPaul Fertser
Change-Id: Iaaa54aee6a74f0b250b83c53e7a3fb7c17718920 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3895 Tested-by: jenkins
2018-01-13target: arm: disassembler: decode v6T2 ARM DSB instructionPaul Fertser
Change-Id: Id91b1a87d34982c72f2a8ab46564c961d1fef9dc Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3894 Tested-by: jenkins
2018-01-13target: arm: disassembler: add v5T Thumb BLX decodingPaul Fertser
Reported by thesourcerer on IRC. Change-Id: I36d4d95de176a19fdd0bf80d8b419be6ca637e98 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3893 Tested-by: jenkins
2018-01-11arm_adi_v5: fix regression from 4553abf9064fe3c0e4ea2ed29a1d2217df74ff5fTomas Vanek
Functions mem_ap_read() and mem_ap_write() incremented address even if addrinc=false. I overlooked this fact and moved mem_ap_setup_tar() set wrong addresses in no-incr mode. Fixed by preventing address increment in no-incr mode. Change-Id: I512e12a6a64e30cf6bc5bf77e3d57d35cc33e058 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Suggested-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/4326 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-01-09aarch64: fix crash on single-steppingMatthias Welwarsky
Make sure to skip un-examined targets (e.g. targets with deferred examination) on single-stepping fixes bug #158 Change-Id: Ib40c6fee03079fd078bd52a84615e6f8a081d128 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4184 Tested-by: jenkins Reviewed-by: Yao Qi <qiyaoltc@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-05arm_adi_v5: reduce some CSW writesTomas Vanek
MEM-AP access through banked data registers MEM_AP_REG_BD0..3 does not increment TAR regardless of the current autoincrement mode. mem_ap_read_u32() and mem_ap_write_u32() can keep the current autoincrement mode instead of switching autoincrement off. Change-Id: Ib7ec688d3e04f1da678363cd2819ce90e8910e58 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4163 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-22 06:04:19 +0000