aboutsummaryrefslogtreecommitdiff
path: root/src/target
AgeCommit message (Collapse)Author
2017-09-22Some hack for MIPS, don't remember the detailsmips-hack-upstreamDavid Barksdale
2017-07-07mips32: inline functions in headers must be staticAndreas Fritiofson
Change-Id: If1d0fc6766cadc2db33408ae5c0968de6b7a1b94 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/4178 Tested-by: jenkins Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-by: Stian Skjelstad <stian@nixia.no>
2017-06-30target: Fix snprintf format string and argument mismatch in md outputAndreas Fritiofson
Commit 47b8cf842 changed the fixed type of the value argument to snprint but didn't change the format string to match for sizes != 64 bit. Change-Id: I908b06f49ab69d04224282949190a0de883048e0 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/4167 Tested-by: jenkins Reviewed-by: Stian Skjelstad <stian@nixia.no> Reviewed-by: Philipp Guehring <pg@futureware.at>
2017-05-31flash: Add support for Atheros (ath79) SPI interfaceTobias Diedrich
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558 Extended and revised version of my original patch submitted by Dmytro here: http://openocd.zylin.com/#/c/3390 This driver is using pure SPI mode, so the flash base address is not used except some flash commands (e.g. "flash program") need it to distinguish the banks. Example config with all 3 chip selects: flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2 Example usage: > flash probe flash0 Found flash device 'win w25q128fv' (ID 0x001840ef) flash 'ath79' found at 0x00000000 > flash probe flash1 No SPI flash found > flash probe flash2 No SPI flash found > flash banks > flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000 reading 4096 bytes from flash @0x00000000 wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset 0x00000000 in 28.688066s (0.139 KiB/s) Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8 Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de> Reviewed-on: http://openocd.zylin.com/3612 Tested-by: jenkins Reviewed-by: Dmytro <dioptimizer@hotmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-08mips32, use scan32 function for reading impcode/idcode.Salvador Arroyo
There is no need to implement scan code in functions mips_ejtag_get_idcode/impcode(), use mips_ejtag_drscan_32(). Impcode/idcode saved in ejtag.info. Reorder the code in the callers of this functions. Change-Id: Ia829c783a0b24c6a65cade736113fa6f67b0a170 Signed-off-by: Salvador Arroyo <salvador@telecable.es> Reviewed-on: http://openocd.zylin.com/4003 Tested-by: jenkins Reviewed-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32: add micromips breakpoints supportSalvador Arroyo
Breakpoint setting based on length (kind) only. Added 16bit aligned 32bit software breakpoints support and same filtering before setting breakpoint. Set the required isa bit in hardware breakpoints. Drop the isa bit in software breakpoints. Change-Id: I7020f27be16015194b76f385d9b8e5af496d0dfc Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4124 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32: add micromips isa handlingSalvador Arroyo
Read and save configuration registers, up to 4. Config3 holds the micromips implementation info. Added isa implementation info to mips32_common. Added isa filter to avoid common mistakes, but only if one isa mode is implemented. When resuming the isa requested is set if more than one isa mode is implemented. Change-Id: I1d6526c5525bffac8d75e031b842b2edc6310e28 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4123 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, convert miniprograms with code definitionSalvador Arroyo
Needed to run in micromips mode. Seems that if an isa is supported in debug mode it also supported in kernel mode. The contrary is not true. Change-Id: I1feb8e2c376f4db97089f05c20bc0cd177208fb3 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4033 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add support for micromips in debug modeSalvador Arroyo
Micromips is 16bit oriented, branch and jumps are 16 bit based. The upper half 16bits of a 32bit instruction with the major opcode, must go first in the instruction stream, hence the SWAP16 macro and swap16 array function, needed if the code is written as 32 bit word in little endian cores. Endianess info added to ejtag_iinfo. Pointer to ejtag_info and isa field added to pracc context. MIPS32 code are renamed to MIPS32_ISA_... To select the isa, the new code has an additional isa parameter (1 for micromips, 0 for mips32). In JR instruction the isa bit must be set to execute micromips code. The suffix u is added to the OP codes to avoid signed/unsigned comparison errors and to make sure the right shift is performed logically. The isa in debug mode is updated in the poll function. Code for miniprograms, in kernel mode, need to be converted. CFI code only for mips32. Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4032 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add microMips instruction subsetSalvador Arroyo
Only reencoded MIPS32 instructions. Added some instructions for crc code. Micromips isa in debug mode is only needed for pic32mm cores. Pic32mz seems that only works with MIPS32 isa when in debug mode. Change-Id: I07059e153a7000ea9204f20b6b37edf6a7623455 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4022 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add option to avoid check in last instructionSalvador Arroyo
This option is needed, for example, when exiting debug mode in bmips targets. The last instruction is a NOP, not a DERET. When working in async mode this check is not done, mips32_pracc_queue_exec() pass the parameter to mips32_pracc_exec() and never use it. Change-Id: I4c7ed4feb1588b62e2645b955b501b6671113b36 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4021 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add realloc codeSalvador Arroyo
If max_code is reached realloc memory. If fails to realloc the error is propagated and every call to pracc_add() returns immediately. The exec function logs the error. Change-Id: Idd4ed9d9b8b19b7d6842d0bc5ebb05f943726705 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4020 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, change in pracc_list for dynamic allocationSalvador Arroyo
pracc_list points to an array with code in the lower half and addr in the upper half. Change it to a struct with an instruction field and an address field. Requiered to make reallocation easier. As a side effect the code is less quirky. Change-Id: Ibf904a33a2f35a7f69284d2a2114f4b4ae79219f Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4019 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-02Fix compile failure on MacOSXMatthias Welwarsky
MacOSX tool chain defines __unused in "sys/cdefs.h", causing a collision. Remove the local define to avoid polluting the compilers internal symbol namespace. Change-Id: I16370c4518e6aeec482dd689e7db80628f846ee3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4118 Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2017-04-25mips32, write handler code in a more compact waySalvador Arroyo
Less code and probably cleaner. Don't check if it is ever ERROR_OK. Change-Id: I1045b58fd4542ec24430332f49679364ae97b1dc Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4018 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-25mips32, implement assembler li instructionSalvador Arroyo
Implement it as a function, the code was already in. Added optimize option. Change-Id: Ib9ad3f00d6c4f0b91c4e4960a50ec8d102f4e333 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4017 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-25mips32, in wait_for_pracc_rw() use ejtag_info->pa_ctrlSalvador Arroyo
Makes code shorter In fasdata transfer fuction declare variables locally. Avoid cast. Change-Id: I0367b66339560fc20521a0598488e7ff9076808e Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4011 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-25mips32, mips32_pracc_finish() queued onlySalvador Arroyo
In most of the cases there is no need to request execution, the check for a new pracc access already does it. Requesting execution if not needed makes execution slower and code larger due the additional checks. Reduce code in fasdata transfer function. Call for execution when exiting debug. Change-Id: I3b45f6d1f62da5fad3e3db84f82a9299b16e1bd9 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4010 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-25mips32, drop unnecessary code in mips32_pracc.cSalvador Arroyo
Struct mips32_pracc_context no more in use. In current code cp0 reg/sel do not requires special handling. In sync mode ctx.store_count not used, drop check. In fasdata transfer function use mips32_pracc_read_ctrl_addr() to reduce code. Change-Id: Ibd4cfa5a44ebc106ed0db042f4e54a2e0b3d43cb Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4007 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-25mips32, homogenize code in the scan functionsSalvador Arroyo
Change-Id: I32fed3332857737048dd12da94fcaba140acb726 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4006 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24mips32, add generic scan 32 functionSalvador Arroyo
Will be used later, allow queuing all needed scans in a pracc access. This makes faster execution with ftdi based adapters working in sync with pracc. Added now because the overall code is shorter. Change-Id: Ib32b89307b75785f88870db8d7c9255dc5bbd426 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4005 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24mips32, pic32 use uint8_t in 8 bit scan functionSalvador Arroyo
Makes code shorter. Change-Id: I6cc01adffbea063ccb071ddf3a3e3d81727b29ce Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4004 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-23target: Fix memory leakMarc Schink
Change-Id: Ib23dfd653d8edacb890a46179e9d437c027d58e8 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4048 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Chengyu Zheng <chengyu.zheng@polimi.it> Reviewed-by: Andreas Färber <afaerber@suse.de>
2017-04-02aarch64: clear CTI halt event early at debug entryMatthias Welwarsky
The halt event was left pending in the CTI, better to clear it immediately after debug entry. Change-Id: I6002f862681baf98769e3c73332a7f7f0ef938c1 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4030 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-03-06arm_dpm: fix dpm setupGirts Folkmanis
When ARM64 support was being merged, a comparison ended up being inverted. This causes NULL pointer access when target attempts to use core cache. Change-Id: Ic8873ddd13dbdd8100856a71b4717f44cd336e23 Signed-off-by: Girts Folkmanis <opensource@girts.me> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4042 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24armv8_dpm: fix exception handlingMatthias Welwarsky
after handling of an exception in debug state, immediately restore the original core state. Change-Id: Ie53b63c9f19815f717f4df4390fbc13f0a204cc2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3996 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24armv8_dpm: retrieve only necessary registers on haltMatthias Welwarsky
to speed up debugging, don't load the complete register context on a halt event, load only those registers that might be clobbered during debugging. Change-Id: I0b58e97aad6f28aefce4a52e870af61e1ef1a44f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3995 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24armv8: spelling and formatting updatesMatthias Welwarsky
small changes to correct code formatting and spelling of some log messages. Change-Id: I645e675f8f9f4731b0271ddc55f64e8cf56ec1db Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3994 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: run control reworkMatthias Welwarsky
This patch contains a major overhaul of the target run control, mainly for the sake of satisfying gdbs ideas of how a target should respond to various control requests for the debugger. The changes allow gdb a slightly better control on how cores are stepped: a core can be single-stepped while other cores remain halted or continue normal execution until the single-stepped core halts again. Also, on any halting event (user command or breakpoint) the system is brought into a stable state with all cores halted before the halt is signaled to the debugger. This patch also transitions the target code to make use of the new CTI abstraction instead of accessing CTI registers directly. Change-Id: I8ddc9abb119e04580d671b57ee12240c3f5070a0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3993 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: clean up struct aarch64_commonMatthias Welwarsky
remove some rarely or completely unused components. Change-Id: Id285bb7075901016297fa173a874db7f11a840d7 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3992 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: clean up target specific commandsMatthias Welwarsky
- rename "cortex_a" command group to "aarch64" - remove default blank check, checksum and algorithm hooks since they're not going to work in aarch64 mode anyway. Change-Id: Ieb0046786ed9425baf6774c68f42a8285cc2aefd Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3991 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: reset fixesMatthias Welwarsky
Make sure all core register caches are invalidated on reset assert, make sure to re-init debug registers on deassert. Change-Id: I82350d04cc3eaae5e35245d13d6c1fb0a8d59807 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3990 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24armv8: factor out generic bit set/clr for debug registersMatthias Welwarsky
introduce armv8_set_dbgreg_bits() function to make register bit-field modifications easier to read. Change-Id: I6b06f66262587fd301d848c9e0645e8327653de7 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3989 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24armv8: load aarch32 register through aarch64 equivalentMatthias Welwarsky
The aarch32 register cache is only a separate view of the aarch64 registers. Load aarch32 registers through their aarch64 equivalents. Change-Id: I3e932dfb782f03d73d30d942b24db340a5749e47 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3988 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: remove bogus address check before memory accessMatthias Welwarsky
Mmu faults can not be prevented on aarch64, they need to be taken and handled accordingly. Remove the remaining stub code. Change-Id: I6241efa594fe6b963624f9628cdf1c8e46588223 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3987 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24target: generic ARM CTI function wrapperMatthias Welwarsky
Not specific to ARMv8, the Cross Trigger Interface deserves an independent access wrapper. Change-Id: I84f8faad15ed3515e0fff7f6cc5d1109ef91a869 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3986 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: optimize core state detectionMatthias Welwarsky
Replace loop by right-shift. Inspired by patch from Alamy Liu Change-Id: I1285f4f54c0695a93fa42e9863ed8ffa4de00f70 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3985 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: reduce debug output to improve legibilityMatthias Welwarsky
Suppress some very verbose LOG_DEBUG's that are not really useful any more. Change-Id: I67f10ba9510a9e34a027f378f4b62b8901ddc8a4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3984 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: remove mrs/msr functions from struct armMatthias Welwarsky
No longer needed, no users. Change-Id: I0cc82a0ef11e1b72101fa9145f014e5d5d76df0e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3983 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: refactor SCTLR manipulationMatthias Welwarsky
Reduce SLOCs in SCTLR retrieval and modification functions and make them less complex. Change-Id: Ida1a99c223743247f171b52eef80dc9886802101 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3982 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: fix software breakpoints when in aarch32 stateMatthias Welwarsky
Use the correct opcode for Aarch32 state, both for the breakpoint instruction itself and the cache handling functions. Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3981 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-15aarch64: Fix #include guardsMarc Schink
Change-Id: I9445b04a210dcde5f8a7cf1560ef23eb53149178 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3975 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-10aarch64: don't try resuming if target is not haltedMatthias Welwarsky
At framework level, the resume hook is not protected. Make sure to not attempt a resume if the target is not halted. Change-Id: I4dd1975a95d6c513bd4f4e999e496bc11182a97a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: don't segfault on reset when target is not examinedMatthias Welwarsky
Basically port a fix that was already done for the cortex_a target. Change-Id: I4cf4519159bda03ed611bc0b2e340a5dad2d85fe Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use cached value of dscr register where neededMatthias Welwarsky
Instead of supplying a local, preinitialized "dscr" variable, use the cached value from arm_dpm, which is kept up-to-date anyway. Change-Id: I06d548d4dc6db68b9d984c83ed026fa9069d7875 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove arm command chain from aarch64 target commandsMatthias Welwarsky
arm commands are mostly unusable anyway, remove them. to be replaced by aarch64 specific commands later Change-Id: Ie994771bc0e86cff1c26f68f1f51ce8ec352a509 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove "mrs <Xt>, currentel" opcodeMatthias Welwarsky
"currentel" special register is not accessible in debug state. Change-Id: I9022b01b423cd9ae8227ed018d6166078ba44832 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove unused struct componentsMatthias Welwarsky
remove unused register index array from armv8_mode_data[] Change-Id: I686c20eeb3da413f5e9ef6058e31ce939741afb4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: improve debug outputMatthias Welwarsky
Make debug and error messages more informative, fix spelling and formatting errors Change-Id: I7245f42c5153bcc95676270814d30e91c113aaed Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: enlarge value buffer of arm_reg to store 64 bitMatthias Welwarsky
struct arm_reg::value[] must be 8 byte to hold a 64bit register value. Change-Id: If253e90731d0ee855eafd9d7b63b91f84630cc7c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-16 17:19:14 +0000