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2019-05-14helper/command: change prototype of command_print/command_print_samelineAntonio Borneo
To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-14target/mips_m4k: change prototype of mips_m4k_verify_pointer()Paul Fertser
To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should be ready to switch to CMD as first parameter. Change prototype of mips_m4k_verify_pointer() to pass CMD instead of CMD_CTX. This change was part of http://openocd.zylin.com/1815 from Paul Fertser and has been extracted and rebased to simplify the review. Change-Id: I9fa3e883d2ca9cc858caaefd33586f78638702f5 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5063 Tested-by: jenkins
2019-03-27smp: move sub-command "smp_gdb" in file smp.cAntonio Borneo
The code for this command is currently replicated in cortex_a and in mips_m4k and is going to be added again for cortex_m. Plus, it is going to be obsoleted by the HW thread pseudo RTOS. Consolidate in smp.c a single instance of the command. This will simplify both obsoleting it and adding it to cortex_m, whatever change comes first. Change-Id: I03cd857e21fa3f7202fdcee36bcbd5aae30a609d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4991 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-27smp: replace commands smp_on/smp_off with "smp [on|off]"Antonio Borneo
Seams over-engineered having two separate commands to turn SMP on/off. Plus it is missing the possibility to dump the current status of SMP and would be weird adding an additional command for it. Moreover, such commands are replicated in few targets so it would make sense centralizing them. - Deprecate the commands "smp_on" and "smp_off". - Add a new command "smp" that accepts optional parameters "[on|off]" and prints the SMP status when run without parameters. This replaces the two commands above. - Put the deprecated and the new command handlers in smp.c - Update the documentation, except for mips_m4k, since it is not available yet. - Promote the macro foreach_smp_target to global context and use it where possible. Change-Id: Ia72841c1a3bd6edd4db4cc809046322f498617e6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4615 Tested-by: jenkins Reviewed-by: Graham Sanderson <graham.sanderson@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-14target/mips: Use 'bool' data typeMarc Schink
Change-Id: Ifb114bfc062ed7c0ff6e4f37a1a6d546f5415344 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4970 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2018-07-31mips_m4k: add optional reset handlerOleksij Rempel
In some cases by using SRST we can't halt CPU early enough. And option PrRst is not available too. In this case the only way is to set BOOT flag over EJTAG and reset CPU or SoC from CPU itself. For example by writing to some reset register. This patch is providing possibility to use user defined reset-assert handler which will be enabled only in case SRST is disabled. It is needed to be able switch between two different reset variants on run time. Change-Id: I6ef98f1871ea657115877190f7cc7a5e8f3233e4 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4404 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-06-22mips_m4k.c: Fix build with --disable-target64Liviu Ionescu
Replace PRIx64 with TARGET_PRIxADDR to avoid build problems when --disable-target64 is used during configure. Change-Id: I054a27a491e86c42c9386a0488194320b808ba96 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4566 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Tim Newsome <tim@sifive.com>
2017-05-08mips32, use scan32 function for reading impcode/idcode.Salvador Arroyo
There is no need to implement scan code in functions mips_ejtag_get_idcode/impcode(), use mips_ejtag_drscan_32(). Impcode/idcode saved in ejtag.info. Reorder the code in the callers of this functions. Change-Id: Ia829c783a0b24c6a65cade736113fa6f67b0a170 Signed-off-by: Salvador Arroyo <salvador@telecable.es> Reviewed-on: http://openocd.zylin.com/4003 Tested-by: jenkins Reviewed-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32: add micromips breakpoints supportSalvador Arroyo
Breakpoint setting based on length (kind) only. Added 16bit aligned 32bit software breakpoints support and same filtering before setting breakpoint. Set the required isa bit in hardware breakpoints. Drop the isa bit in software breakpoints. Change-Id: I7020f27be16015194b76f385d9b8e5af496d0dfc Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4124 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32: add micromips isa handlingSalvador Arroyo
Read and save configuration registers, up to 4. Config3 holds the micromips implementation info. Added isa implementation info to mips32_common. Added isa filter to avoid common mistakes, but only if one isa mode is implemented. When resuming the isa requested is set if more than one isa mode is implemented. Change-Id: I1d6526c5525bffac8d75e031b842b2edc6310e28 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4123 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add support for micromips in debug modeSalvador Arroyo
Micromips is 16bit oriented, branch and jumps are 16 bit based. The upper half 16bits of a 32bit instruction with the major opcode, must go first in the instruction stream, hence the SWAP16 macro and swap16 array function, needed if the code is written as 32 bit word in little endian cores. Endianess info added to ejtag_iinfo. Pointer to ejtag_info and isa field added to pracc context. MIPS32 code are renamed to MIPS32_ISA_... To select the isa, the new code has an additional isa parameter (1 for micromips, 0 for mips32). In JR instruction the isa bit must be set to execute micromips code. The suffix u is added to the OP codes to avoid signed/unsigned comparison errors and to make sure the right shift is performed logically. The isa in debug mode is updated in the poll function. Code for miniprograms, in kernel mode, need to be converted. CFI code only for mips32. Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4032 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-02-10target: Add 64-bit target address supportDongxue Zhang
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-10-04mips: Added #define for scan_delay legacy mode default valueKent Brinkley
Believe in using defines to make maintenance easier. Change-Id: I8edf151352131bbf2b884dfcd67ca5764b11b13c Signed-off-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com> Reviewed-on: http://openocd.zylin.com/2350 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-24Remove FSF address from GPL noticesMarc Schink
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-05MIPS32 Fix typosSalvador Arroyo
I suppose 0xff300008 is the correct value for EJTAG_V20_DBS. 20 miliseconds is too much for scan delay, 2ms is enough in mips_m4k scan_delay handler. mips32 scan_delay has the correct value. Change-Id: Ie9dc650065a58e845687058a4c930f85909beec9 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/2271 Tested-by: jenkins Reviewed-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2016-05-05target: improve robustness of reset commandTomas Vanek
Before this change jim_target_reset() checked examined state of a target and failed without calling .assert_reset in particular target layer (and without comprehensible warning to user). Cortex-M target (which refuses access to DP under active SRST): If connection is lost then reset process fails before asserting SRST and connection with MCU is not restored. This resulted in: 1) A lot of Cortex-M MCUs required use of reset button or cycling power after firmware blocked SWD access somehow (sleep, misconfigured clock etc). If firmware blocks SWD access early during initialization, a MCU could become completely inaccessible by SWD. 2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive to SWD, reset command does not work even if it could help to restore communication. Hopefully this scenario is not possible under full JTAG. jim_target_reset() in target.c now does not check examined state and delegates this task to a particular target. All targets have been checked and xx_assert_reset() (or xx_deassert_reset()) procedures were changed to check examined state if needed. Targets except arm11, cortex_a and cortex_m just fail if target is not examined although it may be possible to use at least hw reset. Left as TODO for developers familiar with these targets. cortex_m_assert_reset(): memory access errors are stored instead of immediate returning them to a higher level. Errors from less important reads/writes are ignored. Requested reset always leads to a configured action. arm11_assert_reset() just asserts hw reset in case of not examined target. cortex_a_assert_reset() works as usual in case of not examined target. Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2606 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-08-19mips_m4k.c: EJTAGBOOT and NORMALBOOT are not supported on EJTAG 2.0Oleksij Rempel
Change-Id: I8157c19e9d8aed5c2376a2c54c32c1ddac1ad5af Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1934 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-08-19mips_m4k.c: D or I breaks only if they supported.Oleksij Rempel
For example Realtek RTL8186 (Lexra LX5280 core) don't support break- and watchpoints. Change-Id: Ie00102da4bf13a8c42a9ad05910c66884f297cfd Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1933 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-07-10mips_m4k.c: make sure fast_data_area is safeOleksij Rempel
If load_image address overlap with fast_data_area, it will caouse different mysterius issues. This patch should prevent it. Change-Id: Ibc95e5aa3ac002a59755029496b6a72616e9287f Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1854 Tested-by: jenkins Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31Clean up const usage to avoid excessive castingAndreas Fritiofson
Don't use const on pointers that hold heap allocated data, because that means functions that free them must cast away the const. Do use const on pointer parameters or fields that needn't be modified. Remove pointer casts that are no longer needed after fixing the constness. Change-Id: I5d206f5019982fd1950bc6d6d07b6062dc24e886 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1668 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31Clean up many C99 integer types format specifiersPaul Fertser
This eliminates most of the warnings reported when building for arm-none-eabi (newlib). Hsiangkai, there're many similar warnings left in your nds32 files, I didn't have the nerve to clean them all, probably you could pick it up. Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1674 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-09-08target: remove unimplemented target_request_data implementationsSpencer Oliver
Change-Id: Ia9afa83752d17f0f56bdf3bd81f5c69d108aa5e9 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1537 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-09-08target: remove unimplemented soft_reset_halt implementationsSpencer Oliver
Let the default handler issue an unsupported warning rather than using empty handler routines that may/may not issue a unsupported warning. Change-Id: Iafe3e45146981a4cfae39771c3ab7370ac86da48 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1535 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
2013-07-17mips: add breakpoint support for EJTAG 2.0Oleksij Rempel
EJTAG 1.5, 2.0 and 2.5 have different breakpoint register addresses. This patch add support of EJTAG 2.0, which is part some broadcom SoCs. This work was testet on Broadcom BCM7401. Change-Id: I4b0ee23871fa9205f9001b7c9165e7b6ebe9ccbf Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1464 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-12[RFC] mips: Enable bulk write optimization for all writesAndreas Fritiofson
mips_m4k_bulk_write_memory was only called from target_write_buffer as an optimization when the word count was large enough. Remove mips_m4k_bulk_write_memory from the target type, causing the default implementation to call the regular mips_m4k_write_memory instead. Perform the dispatch to bulk write in mips_m4k_write_memory, enabling the optimization for target_write_memory() writes with size 4, in addition to target_write_buffer() writes. It also enables making the choice of bulk write vs regular write specifically for the architecture and not relying on the generic target code to make a sensible decision. Change-Id: I295f21a67ceaa195802403f2518ea2e0a025c1c7 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1215 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
2013-06-05update files to correct FSF addressSpencer Oliver
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 3Salvador Arroyo
Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified. mips32_cp0_read() is very similar to mips32_read_u32() with one store access. mips32_pracc_read_regs() is the only function that can not be executed from only one queue. Now this function is modified to use reg8, it saves all the registers but does not restore reg8. To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and restore it from ejtag info instead of using DeSave for save/restore. Change-Id: Icc224f6d7e41abdec94199483401cb512cc0b450 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1195 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 1Salvador Arroyo
This patch and the following patches define another way of doing processor access without the need to read back the pracc address as needed in current pracc code. Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200 and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start. Most of the processor accesses are fetch and some are store accesses. After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses. The pracc address for a store depends only on the store instruction given before. m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline. For reference: MD00249 mips32 m4k manual. A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by current code or by the new one to generate the sequence of pracc accesses. For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96(). This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution. The pracc bit is not checked before execution, is checked after the queue has been executed. Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay between scans is added by calling jtag_add_cloks(). A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it. A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set, current code is executed, if lower, new code is executed. Initial default values are set in function mips32_init_arch_info. A reset does not change this settings. Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1193 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-02mips: code cleanup in cp0 command handlersSalvador Arroyo
After calling mips32_cp0_read() nothing has been queued, the call to jtag_exec_queue() is unnecessary. Change-Id: Ie25438045a8e9b6b1b170df7b52609d45f284b5a Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1190 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02mips: change in restoring debug working registerSalvador Arroyo
In current devel code there are 3 functions (related to m4k code) that need to restore register 8 from pracc stack: mips32_pracc_read_u32() mips32_cp0_read() mips32_pracc_write_mem_generic() And mips32_pracc_read_mem() needs to restore regs 8 and 9 from pracc stack. Values in this registers should be the same as read by mips32_pracc_read_regs() when entering debug mode and can be modified by mips32_pracc_write_regs() when leaving debug mode. There is no need to read their values from the processor registers every time. The fields reg8 and reg9 are added to struct mips_ejtag to store these register values and the call to mips32_save_context() is shifted in mips_m4k_debug_entry() in order to store them before any other function needs to restore these registers. For the same reason in function mips_m4k_step() the call to mips_m4k_set_breakpoint(), if needed, should be made after calling mips_m4k_debug_entry(). For single word write the number of pracc accesses are now 9 or 8, from 13 or 12 in current code, single word read takes now 10 instead of 12. This patch is really the first in a set of patches for an alternate m4k pracc code much faster that current code. At least for me with pic32mx works fine. Change-Id: Ibd9df5e8b9f78ce05a180949ba6a561c761b61d6 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1146 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-11mips_m4k: Fixed mips_m4k_resume code for smp targetsKamal Dasu
Fix for bug introduced in in mips smp support code in the resume logic that is checking for wrong return value. Change-Id: Ice3e0069f936b556fecc338ccc12ddba38deeaf6 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1048 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09mips_m4k: Added SMP debug support for mips architecturesKamal Dasu
This change adds smp debug support for mips platforms. The change leverages the exiting gdb smp support as mentioned in the OpenOCD documentation for using gdb in smp environemnt. Added commands smp_on, smp_off, smp_gdb to control the smp mode. The implementation also provides a way to send Jc packet and toggle the gdb display core context as well. Change-Id: I0835a5aed1844b6ebf8291582912f20695346003 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/937 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: code clean up in mips_m4k_debug_entry() functionSalvador Arroyo
The function mips_ejtag_read_debug() is defined in mips_ejtag.c and is called only by mips_m4k_debug_entry() for reading the CP0 debug register. The comment in this function is obviously wrong. There is a generic function to read CP0 registers with similar code. A call to mips32_cp0_read() should work in the same way. The purpose of reading the debug register is to test if the DSS bit is set and clear the SSt bit. It is faster and easier if the SSt bit is cleared without any check. Remark: DSS bit set only means that a debug single-step exception ocurred, but it is not possible to step over a sdbbp instruction, in this case DSS will not be set and the SSt bit not cleared by code. Resume command at another address will step, so really the behavior is not the same. Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/950 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-05-14mips: support connecting under resetSpencer Oliver
Some targets support connecting while the target's srst is asserted. Tested on pic32 family. Change-Id: I0d20c40af6d031d1306043893e95e61f484c0a87 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/608 Tested-by: jenkins
2012-03-14mips: Forced to running state to enable (subsequent) target halt.Drasko DRASKOVIC
Change-Id: I9aff8fb3ac703b50194088dd4e68cec8f9bb2ada Signed-off-by: Drasko DRASKOVIC <drasko.draskovic@gmail.com> Reviewed-on: http://openocd.zylin.com/513 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-03-13target: remove unused declarationSpencer Oliver
arm7_9_prepare_reset_halt is long since gone and the functionality is implemented in the target's assert_reset handler. Change-Id: Ib03c730cb39d68e5e3bb42f92af13daf8074e4e2 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/515 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
2012-02-06build: cleanup src/target directorySpencer Oliver
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-18cmd: add missing usage varsSpencer Oliver
we should have caught them all - hopefully. Change-Id: I35435317fccaf5ad0216244d69f76db6857bb582 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/381 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-01-04Change return value on error.Mathias K
On wrong parameters a error is signalized to the calling function. Change-Id: I484443fdb39938e20382edc9246d5ec546a5c960 Signed-off-by: Mathias K <kesmtp@freenet.de> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/282 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-01-04retire ERROR_INVALID_ARGUMENTS and replace with ERROR_COMMAND_SYNTAX_ERRORØyvind Harboe
Change-Id: I6dee51e1fab1944085391f274a343cdb9014c7a4 Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/300 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-08-12mips: fix potential alignment errorStefan Mahr
2011-08-12mips: fix reading uint32 and uint16 when running on big endian hostStefan Mahr
2011-08-09mips32 : Fixed memory byte accessDrasko DRASKOVIC
Function mips_m4k_write_memory() does endianess byte swap, but this procedure break one byte access (temporary array overwrites content in buffer). As a fix, this endianess swap and buffer affecting is preformed only on hword and word accesses (not on byte access).
2011-08-09mips32: Added CP0 coprocessor R/W routinesDrasko DRASKOVIC
This patch adds MIPS32 CP0 coprocessor R/W routines, as well as adequate commands to use these routines via telnet interface. Now is becomes possible to affect CP0 internal registers and configure CPU directly from OpenOCD.
2011-07-04mips_m4k and arm7_9 : Fix soft bkpt endianess for 16-bit instructionsDrasko DRASKOVIC
The patch fix comparison of target data on the host by using target_buffer_get_u16() to transform current_instr to _host_ endianess before comparison.
2011-07-01mips_m4k : Fix soft breakpoint endianess handlingDrasko DRASKOVIC
In order to compare data read from the target with some marcros or data defined on the host, we must transform this read data from target endianess to host endianess. target_read_memory() gets bytes from target to the host, but keeps them in _target_ endianess. This is OK if we just want to temporary keep this data on the host, like keeping breakpoint->orig_instr. But if we want to use this data for any ispections and comparisons on the host side, we must transform it to _host_ endianess, by using target_buffer_get_u32() function. Currently this transformation is missing, and check current_instr == MIPS32_SDBBP will never pass if target and host endianess differ, because current_instr will be kept in _target_ endianess and MIPS32_SDBBP will be kept in _host_ endianess, The patch fix this issue by using target_buffer_get_u32() to transform current_instr to _host_ endianess before comparison.
2011-06-28mips4k: fix big-endian hosts and host alignment problemsØyvind Harboe
the code was making assumptions about the endianness of the host.
2011-06-01mips: fix some more endian madnessStefan Mahr
2011-04-05Added mips_ejtag_drscan_32_out() for optimization.Drasko DRASKOVIC
2011-04-05Added correct endianess treatment for big endian targets. Now it is possible ↵Drasko DRASKOVIC
to use mips_m4k_write_memory() and mips_m4k_read_memory() to correctly set-up SDRAM, as well as bulk data write, which already handled endianess well. Also added correct endianess manipulation in case of fallback from erroneus bulk write to simple write (to avoid byte swapping two times).
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