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Micromips is 16bit oriented, branch and jumps are
16 bit based. The upper half 16bits of a 32bit instruction
with the major opcode, must go first in the instruction
stream, hence the SWAP16 macro and swap16 array function,
needed if the code is written as 32 bit word in little endian
cores. Endianess info added to ejtag_iinfo. Pointer to
ejtag_info and isa field added to pracc context.
MIPS32 code are renamed to MIPS32_ISA_...
To select the isa, the new code has an additional isa parameter
(1 for micromips, 0 for mips32).
In JR instruction the isa bit must be set to execute
micromips code.
The suffix u is added to the OP codes to avoid signed/unsigned
comparison errors and to make sure the right shift is
performed logically.
The isa in debug mode is updated in the poll function.
Code for miniprograms, in kernel mode, need to be converted.
CFI code only for mips32.
Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4032
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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This option is needed, for example, when exiting
debug mode in bmips targets. The last instruction
is a NOP, not a DERET. When working in async mode
this check is not done, mips32_pracc_queue_exec() pass
the parameter to mips32_pracc_exec() and never use it.
Change-Id: I4c7ed4feb1588b62e2645b955b501b6671113b36
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4021
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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If max_code is reached realloc memory. If fails to realloc
the error is propagated and every call to pracc_add() returns
immediately. The exec function logs the error.
Change-Id: Idd4ed9d9b8b19b7d6842d0bc5ebb05f943726705
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4020
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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pracc_list points to an array with code in the lower half
and addr in the upper half. Change it to a struct with
an instruction field and an address field.
Requiered to make reallocation easier.
As a side effect the code is less quirky.
Change-Id: Ibf904a33a2f35a7f69284d2a2114f4b4ae79219f
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4019
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Less code and probably cleaner.
Don't check if it is ever ERROR_OK.
Change-Id: I1045b58fd4542ec24430332f49679364ae97b1dc
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4018
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Implement it as a function, the code was already in. Added optimize
option.
Change-Id: Ib9ad3f00d6c4f0b91c4e4960a50ec8d102f4e333
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4017
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Makes code shorter
In fasdata transfer fuction declare variables locally.
Avoid cast.
Change-Id: I0367b66339560fc20521a0598488e7ff9076808e
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4011
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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In most of the cases there is no need to request execution,
the check for a new pracc access already does it.
Requesting execution if not needed makes execution slower and
code larger due the additional checks.
Reduce code in fasdata transfer function.
Call for execution when exiting debug.
Change-Id: I3b45f6d1f62da5fad3e3db84f82a9299b16e1bd9
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4010
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Struct mips32_pracc_context no more in use.
In current code cp0 reg/sel do not requires special handling.
In sync mode ctx.store_count not used, drop check.
In fasdata transfer function use mips32_pracc_read_ctrl_addr()
to reduce code.
Change-Id: Ibd4cfa5a44ebc106ed0db042f4e54a2e0b3d43cb
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4007
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Define a target_addr_t type to support 32-bit and 64-bit addresses at
the same time. Also define matching TARGET_PRI*ADDR format macros as
well as a convenient TARGET_ADDR_FMT.
In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000)
be least invasive by leaving the formatting unchanged apart from the
type;
for generic code adopt TARGET_ADDR_FMT as unified address format.
Don't silently change gdb formatting here, leave that to later.
Add COMMAND_PARSE_ADDRESS() macro to abstract the address type.
Implement it using its own parse_target_addr() function, in the hopes
of catching pointer type mismatches better.
Add '--disable-target64' configure option to revert to previous 32-bit
target address behavior.
Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Signed-off-by: David Ung <david.ung.42@gmail.com>
[AF: Default to enabling (Paul Fertser), rename macros, simplify]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
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First, fix the timeval_ms() implementation to not have K&R but ANSI
argument semantics by adding a missing void.
timeval_ms() returns an int64_t, not uint64_t or long long. Consistently
use int64_t for variables and PRI*64 as format string.
While at it, change a few related variables to bool for clarity.
Note that timeval_ms() may return a negative error code, but not a
single caller checks for that.
Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3499
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
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Also make GPL notices consistent according to:
https://www.gnu.org/licenses/gpl-howto.html
Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3488
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
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BMIPS always needs 2 additional instructions to reach the core.
Seems there is a 2 instructions fifo between the tap and the core, or it behaves in this way.
No idea of the purpose of this fifo, I can only guess.
Of course function mips32_pracc_clean_text_jump() must add this additional instructions (NOPs).
Only tested on bcm3348..
Change-Id: I3183d3ce865d469d7262ba4b15446e5743a5f1df
Signed-off-by: Salvador Arroyo <salvador@telecable.es>
Reviewed-on: http://openocd.zylin.com/2270
Tested-by: jenkins
Reviewed-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Warnings exposed by arm-none-eabi build.
Change-Id: Icdaf168d7aaa1a62bdfd41a64e43ef94816d3721
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2140
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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This is only the basic code proposed for mips32_pracc_exec() function.
It checks every pracc address against the expected address when
reading (instruction fetch).
The code expects to start at PRACC_TEXT and any subsequent read address
is obtained by adding 4 to the previous one.
After shifting out all the instructions the code executes a final check.
It checks now for the first pass trough PRACC_TEXT and shift out
only NOP instructions.
A mips core does not need an additional NOP and after the first check
it exits if there is no store access pending.
After shifting out one NOP the core must be reading at pracc text or the
code exits with error.
The code continues shifting out NOPs until all store accesses have
been performed.
After shifting out 10 NOPs it exits with error.
No assumption is made about the number of store instruction shifted out or
the ordering of the store accesses. It only checks that the number of
store accesses is the same as the number of store instructions at dmseg
after execution.
mips32_pracc_read_ctrl_addr() and mips32_pracc_finish() are added to
simpify a bit the code. Fields pa_ctrl and pa_addr are added
in ejtag_info for storing values of pracc control and address.
Change-Id: If6322d5c8cbeadcd4acd3972c0f72c8490f53c34
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1827
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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This is the first patch intended to make a more precise pracc check
when running in legacy mode (code executed by mips32_pracc_exec()).
It only makes some cleanups, mostly due to unnecessary code.
With the last cache optimizations for processor access (pa for short)
all the pracc functions generate the code following some rules that
make pa more easily to check:
There are no load instructions from dmseg. All the read pas are
instruction fetches. PARAM_IN related stuff is not needed.
Registers are restored either from COP0 DeSave or from ejtag
info fields. PRACC_STACK related stuff is not needed any more.
The code starts execution at PRACC_TEXT and there are no branch or jump
instruction in the code, apart from the last jump to PRACC_TEXT.
The fetch address is ever known.
For every store instruction to dmseg the function code sets
the address of the write/store pa.
The address of every store pa is known.
Current code ends execution when reading a second pass through PRACC_TEXT.
This approach has same inconveniences:
If the code starts in the delay slot of a jump it makes a jump
to PRACC_TEXT after executing the first instruction. A second pass
through PRACC_TEXt is read and the function exits without any warning.
This seems to occur sometimes when a 24kc core is halted in the delay
slot of a branch.
If a debug mode exception is triggered during the execution of a
function the core restarts execution at PRACC_TEXT. Again the function
exits without any warning.
If for whatever reason the core starts fetching at an unexpected
address the code now sends a jump instruction to PRACC_TEXT, but due
to the delay slot the core continues fetching at whatever address + 4
and a second jump instruction will be send for execution. The result
of a jump instruction in the delay slot of another jump is
UNPREDICTABLE. It may work as expected (ar7241), or let the core in
the delay slot of a jump to PRACC_TEXT for example. This means the
function called next may also fail (pic32mx).
Change-Id: I9516a5146ee9c8c694d741331edc7daec9bde4e3
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1825
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Near all pracc functions store $15 in DeSave and
restore it when exiting.
There is no need to save it, if mips32_pracc_read_regs()
save this register in Desave when entering debug mode.
mips32_pracc_write_regs() needs to update it when
exiting debug mode.
Other pracc functions must not modify DeSave.
The jump code in the fastdata transfer function needs also
some little modifications.
Remark:
Like in current code the user can read/modify $15
with the cp0 31 commands.
Change-Id: I5b7dfc1b6169da846f5d2dd3ad4209a9da2c3fad
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1565
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Currently the code is loaded calling mips32_pracc_write_mem_generic().
Cache synchronization is not performed.
If configured as write back cache there is no chance to execute the
handler. If configured as write through cache and the cache
lines written to are not cache resident (I-side cache miss) may work.
The patch makes possible to execute the handler in a cached active
memory segment (mainly from KSEG0), but nothing else. The data
is still loaded without performing cache synchronization, code loaded
may not be executable.
Performance may not be faster. At start, for example, the code resides in
main memory, not in cache, and the core must transfer code from
memory. We can really modify the code to force a wait for the first
transfer like we do with start and end addresses, making sure the code
is cache resident for the rest of the queued transfers.
This can also may happen if we execute code (greater than the I cache size)
and the handler code is evicted from the cache.
Code tested on ar7241.
Change-Id: Iffdb4dae108b872fef0e7bacc5ea99649cdc1630
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1564
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Follows the the same rules of optimization used by all pracc functions.
Solves some bugs in previous code and adds support for write through caches.
Change-Id: If88c6738ca8c8197f327f22b766120a24f71b567
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1557
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Don't use const on pointers that hold heap allocated data, because that
means functions that free them must cast away the const.
Do use const on pointer parameters or fields that needn't be modified.
Remove pointer casts that are no longer needed after fixing the constness.
Change-Id: I5d206f5019982fd1950bc6d6d07b6062dc24e886
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1668
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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This eliminates most of the warnings reported when building for
arm-none-eabi (newlib).
Hsiangkai, there're many similar warnings left in your nds32 files, I
didn't have the nerve to clean them all, probably you could pick it
up.
Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1674
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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On some CPUs, like bcm7401 with EJTAG v2.0 we can have situation where
CPU do not stops execution. For example, all CP0 commands will have this issue.
In this case we should some hove recover our session. Currently
jump to 0xff20.0200 seems to be good option. If it brake some thing on
newer EJTAG, then check for EJTAG v2.0 should be added.
Change-Id: Icd8841f38a1a85e0f7682b6dc358af8dfaae0744
Signed-off-by: Oleksij Rempel <bug-track@fisher-privat.net>
Reviewed-on: http://openocd.zylin.com/1353
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1426
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
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Now all the functions with only fetch accesses are modified.
The same delay between scans has been added to mips32_pracc_fastdata_xfer(), it should work
at the same scan rates as the other pracc functions, but it needs higher scan_delays
to work.
Change-Id: Ifb31d8ea6de9d22674385782913d221a2494dbbf
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1196
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified.
mips32_cp0_read() is very similar to mips32_read_u32() with one store access.
mips32_pracc_read_regs() is the only function that can not be executed from only one queue.
Now this function is modified to use reg8, it saves all the registers but does not restore reg8.
To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in
mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and
restore it from ejtag info instead of using DeSave for save/restore.
Change-Id: Icc224f6d7e41abdec94199483401cb512cc0b450
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1195
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Each pracc function defines a variable ctx of type struct pracc_queue_info.
To simplify the code tree auxiliary functions are defined: pracc_queue_init(), pracc_add() and
pracc_queue_free().
The second parameter in pracc_add() is the store address if the instruction is a store at dmseg,
otherwise it should be 0.
The code is executed by mips32_pracc_queue_exec(). If ejtag_info->mode is 0 mips32_pracc_exec()
is called and it should work like with current code.
To generate the delay between scans the number of clock ticks are calculated with the help of
jtag_get_speed_khz(). Due to delays in the execution of each single ftdi instruction the number of ticks
are higher as it should be, specially at higher scan rates.
mips32_pracc_read_u32() should now work with the new code.
Change-Id: I471590a4fc89b56af10bd46c48767b4c64de154f
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1194
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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In current devel code there are 3 functions (related to m4k code) that need to restore register 8 from pracc stack:
mips32_pracc_read_u32()
mips32_cp0_read()
mips32_pracc_write_mem_generic()
And mips32_pracc_read_mem() needs to restore regs 8 and 9 from pracc stack.
Values in this registers should be the same as read by mips32_pracc_read_regs() when entering debug
mode and can be modified by mips32_pracc_write_regs() when leaving debug mode.
There is no need to read their values from the processor registers every time.
The fields reg8 and reg9 are added to struct mips_ejtag to store these register values
and the call to mips32_save_context() is shifted in mips_m4k_debug_entry() in order
to store them before any other function needs to restore these registers.
For the same reason in function mips_m4k_step() the call to mips_m4k_set_breakpoint(), if needed,
should be made after calling mips_m4k_debug_entry().
For single word write the number of pracc accesses are now 9 or 8, from 13 or 12 in current code,
single word read takes now 10 instead of 12.
This patch is really the first in a set of patches for an alternate m4k pracc code
much faster that current code. At least for me with pic32mx works fine.
Change-Id: Ibd9df5e8b9f78ce05a180949ba6a561c761b61d6
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1146
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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In this function after loading the handler code and the jump code there is a call
to wait_for_pracc_rw() to verify that a pracc access is pending.
Next the address is read to verify that the handler is running, the address should be at
fastdata area.
Next, another call is made to wait_for_pracc_rw(). This call is not needed, we now already
that a pracc access is pending.
Better we call this function before loading the end address to be sure it is loaded correctly.
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Change-Id: If311450ea634786fc28cf1a8e18ed24ce5257d20
Reviewed-on: http://openocd.zylin.com/1142
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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No function writes to MIPS32_PRACC_PARAM_IN addresses and probably has no much sense.
Any attempt to write to those addresses should be an error.
Change-Id: Iebea5fa9954e2cd56ad34976dd7d25009c6e6388
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/975
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Current code needs 101 pracc accesses for this function, this code needs 12 less.
There is a singularity in this code, is the only function that restore
a register from param out instead from pracc stack. Obviously the register
was previously stored at param out. This save 2 pracc accesses.
Change-Id: Ie95b6f983a3198dafc0eab2dd5acc11f871a8d83
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/958
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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All the the loads are done with lui and ori instructions, there is
no need to save any register, they will be overwritten.
Like in the previous patch, for speed optimization in write code,
same instructions can be saved if the lower half word or the upper
half word is 0.
If the lower half word is 0, it can be loaded with only a lui instruction.
If the higher half word is 0 it can be done with an ori instruction with register 0.
This code saves 10 pracc accesses at a minimum, and 40 at a maximum,
obviously if register 2 to 31 are 0 or a half word is 0
Current code needs 91 pracc accesses.
Change-Id: I892c5b440191d0c7a474c96845d41c373b7fc637
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/957
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
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All the writes are done by the new function mips32_pracc_write_mem_generic().
The code is similar to the read generic code.
The reuse of register 15 as memory base address saves 3 pracc accesses.
The first write takes 13(12) pracc accesses and for additional writes 3(2).
Loading miniprograms should take 25% less time and loading fastdata transfer
handler code should be over 2x faster.
Change-Id: Ia3b24ba084af33be99da19f00a7fd4d1b291f350
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/956
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Really nothing new that not explained in previous patches.
The code is expanded as needed, there are no loops in pracc code.
For the first value pracc accesses are reduced from 39 to 16
and for aditional values from 10 to 3.
dump_image should work around 3x faster.
Change-Id: I37c9b13395c09eb52a91f10cdb6cbaedef8ab98b
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/955
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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This function is highly optimized, there is not much to
improve.
Loading the base address for pracc access with the new
defined MIPS32_PRACC_BASE_ADDR saves one instruction.
The memory address is loaded in too steps. First the upper
address is loaded. The lower address is passed as an offset in
the memory load instruction.
The offset is signed, if the lower address is in the range of
0x8000 to 0xffff the offset is a negative value, and the upper
address must be incremented by 1.
Pracc accesses are now 12 instead of 14.
Change-Id: I286945b240ed5c5d5cc540780a41a8a5fa075da3
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/952
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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MIPS32_PRACC_BASE_ADDR is defined as 0xFF200000. Now is
possible to load the base address with a lui instruction and
only one pracc access.
Offsets to the pracc code addresses are defined to simplify the code
and probably make it a bit more readable or self-explained.
Change-Id: I853dd2d7fad52745931cc6e6be68c0ae156d897e
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/951
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
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The function wait_for_pracc_rw() fails if Pracc bit is 0.
The variable ejtag_ctrl is loaded with the content of the
control register in the first scan.
In the second scan Pracc bit is scanned out as 0, letting
the proccesor go. The result is unpredictable.
All the strange data corruption when scanning at certain
frequencies, or the strange delays needed when entering
or leaving fasdata area are retated to this bug.
Now the code works at any scan frequency, tested up to 15000Khz
and indepently of processor speed, tested at 31.25Khz and 4/8Mhz.
Change-Id: Iedfd81d06d6af4bc738a521f720e42323025b268
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/769
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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When testing a pic32mx220f032b with different values
for adapter_khz and cpu clocks i was getting a lot of
corrupted data from the chip. From time to time
openocd fails with segmentation faults or is aborted
due to memory corruption.
Change-Id: I134743f75c477b3d55dc74ae4474598e153b4a4a
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/690
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Do not call mips32_cp0_read() if not needed.
This will speed up execution of mips_m4k_write_memory()
by near 2x, with parameter count = 1.
Change-Id: I7829a7802b6475bc6d4ac3f0632d8d239d1072da
Signed-off-by: Salvador <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/624
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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This functions are unfinished and work only with parameter count up to 1024.
Commands mdh and mdb from pic32mx context show values not related to memory
content if parameter count is bigger than 1024. Firt 1024 are ok.
Change-Id: Ie3f4d4a0f9d1d1a69bd3a18de2f72dd9249514cb
Signed-off-by: Salvador <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/550
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
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The bug shows up with the command "mdw addres count" and only if count>1024 (count>0x400).
The first 1024 values shows as expected, but the rest of the values are wrong.
Name of variable bytesread" is changed to "wordsread" to reflect what really does.
Change-Id: Iad79393e72da2637551c5ae6e829e3873605c520
Signed-off-by: Salvador <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/527
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/430
Tested-by: jenkins
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Change-Id: I822f3adce0eccb880007673d60c7eccf7d36b398
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/144
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
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Pprogram that loads another program into memory is actually writing the
D- side cache.
The instructions it has loaded can't be executed until they reach the
I-cache.
After the instructions have been written, the loader should arrange to
write back any containing D-cache line and invalidate any locations
already in the I-cache.
For the MIPS Architecture Release2 cores, we can use synci command
that does this job.
For Release1 we must use "cache" instruction.
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This patch adds MIPS32 CP0 coprocessor R/W routines,
as well as adequate commands to use these routines via
telnet interface.
Now is becomes possible to affect CP0 internal registers
and configure CPU directly from OpenOCD.
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jtag_execute_queue() is executed as a part of mips_ejtag_drscan_32().
No need for this to be done before - removed for optimisation.
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that PrAcc is "1" before FASTDATA access.
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accidentally invoked return jtag_execute_queue() in the
middle of a fn. Hmm.... I would have expected gcc or
at least lint to catch this.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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