aboutsummaryrefslogtreecommitdiff
path: root/src/target/cortex_m.h
AgeCommit message (Collapse)Author
2019-06-19Support for debugging on ARMv8-M CPUsOmair Javaid
This patch adds ARMv8-M CPUs detection logic in ARMv7m target specific code. Also adds a slightly different watchpoint manipulation logic for ARMv8-M. This is based on ARMv8-M architecture reference manual. Tested on ARM Musca A board. Change-Id: I0652560954ef02c378a7067fab586edf39d3e9cc Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4997 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-23cortex_m: set the debug reason to DBGRQ when NVIC_DFSR indicates EXTERNALTarek BOCHKATI
By definition the EXTERNAL bit in Debug Fault Status Register indicates that an external debug request (EDBGRQ) signal was asserted. Usage example: this could be done by CTI in multicore devices in order to halt all the cores together. Change-Id: I7830455ce5da6702b7d08c8fa7bfe80e4d8a5055 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5157 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-10target/cortex_m: Implement maskisr steponly optionChristopher Head
`maskisr steponly` disables interrupts during single-stepping but enables them during normal execution. This can be used as a partial workaround for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with FPU (AT611) Software Developer Errata Notice" from ARM for further details. Change-Id: I797a14e4d43f6dcb3706528ee4ab452846ebf133 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4673 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2019-04-01target/cortex_m: remove fp_code_available countingTomas Vanek
fp_code_available looses sync with the real number of free comparators as soon as cortex_m_set_breakpoint() returns an error. Remove the counter and always go through the fp_comparator_list to find a free one. Change-Id: I9f6e06c36d8a57ad11df5155e8a1a3aff6d833a5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4870 Tested-by: jenkins Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-06target/cortex_m: Use 'bool' instead of 'int'Marc Schink
Change-Id: I273d24997e2c844015e144a15981f8f0af522261 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4950 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2018-12-19target/cortex_m: do not use VECTRESET on Cortex-M0, M0+ and M1Tomas Vanek
Cortex-M0, M0+ and M1 do not support VECTRESET bit in AIRCR. Without this change the 'reset' command silently fails if VECTRESET is requested. Detect these cores, show warning if VECTRESET is about to use and use SYSRESETREQ instead. Change-Id: Ief174373e3ef0e6b287c57911c0aca4dfa8209f2 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4794 Tested-by: jenkins Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2018-04-12target/cortex_m: allow setting the type of a breakpointTomas Vanek
Cortex-M target used 'auto_bp_type' mode. The requested type of breakpoint was ignored and hard (FPB) breakpoints were set in 'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above 0x20000000. The code memory area of Cortex-M does not mean the memory is flash and vice versa. External flash (parallel or QSPI) is usually mapped above code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis has a RAM block under 0x20000000 boundary. Remove 'auto_bp_type' mode, set breakpoints to requested type. Change 'cortex_m maskisr auto' handling to use a hard temporary breakpoint everywhere: it can also workaround not working soft breakpoints on Cortex-M7 with ICache enabled. Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4429 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-13hla_target: allow non-intrusive profiling on cortex-mKarl Palsson
Leverages the existing work that added profiling via DWT_PCSR. hla_target doesn't have direct access to the mem_ap for doing a bulk repeated read, but simply reading the DWT_PCSR register repeatedly is still ~2 order of magnitude faster than halt/resume. Change-Id: Ibe451aa95143694398370fdad6939cfb6191d56f Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/4220 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13cortex_m: add profiling functionSimon Schubert
Use DWT_PCSR if present (reads nonzero); otherwise do halt-and-sample pc. Signed-off-by: Simon Schubert <2@0x2c.org> Change-Id: Id2dc4665e5008cc497a2e6e6493522d038d5af42 Reviewed-on: http://openocd.zylin.com/4211 Tested-by: jenkins Reviewed-by: Karl Palsson <karlp@tweak.net.au> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08cortex_m: allow setting debug ap during createMatthias Welwarsky
This patch adds a Cortex-M private configuration option that allows setting the acess point during target creation. This circumvents situations in hybrid systems when the correct access point can not be automatically detected. Change-Id: If313a5250e6e66509bb9080f3498feab7781dced Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3639 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-05-24Make #include guard naming consistentMarc Schink
Change-Id: Ie13e8af0bb74ed290f811dcad64ad06c9d8cb4fa Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2956 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-24Remove FSF address from GPL noticesMarc Schink
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29target/arm: Remove usage of struct arm_jtag in ARMv7 targetsAndreas Fritiofson
The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be able to pass a pointer to it to one common JTAG function which anyway only uses the TAP field. Refactor the function to take a TAP directly, remove the legacy struct from cortex instances and store the TAP pointer only in the DAP. Cortex-M makes a call to arm_jtag_setup_connection() with the struct but the function does nothing useful for a Cortex-M target so remove the call. Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3142 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-10-30Cortex-M: Detect Flash Patch Revision and implement Rev. 2 handling.Uwe Bonnes
E.g. STM32F7 implements Rev.2. Supercedes abandoned patch 2755 that doesn't evaluate Flash patch revision. Change-Id: I48756b0451c7359475066969c900978a536bc328 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2868 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-03-25armv7m: add generic trace support (TPIU, ITM, etc.)Paul Fertser
This provides support for various trace-related subsystems in a generic and expandable way. Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2538 Tested-by: jenkins
2015-03-09server, target, cortex_m: add deinit_target to the API to free resourcesPaul Fertser
This should facilitate dynamic target creation and removal. Currently it helps with getting 0 bytes lost report from Valgrind on exit (after talking to a nucleo board). However, 1,223,886 bytes in 5,268 blocks are still reachable which means the app holds pointers to that data on exit. The majority comes from the jtag command queue, there're also many blocks from TCL command registration. Change-Id: I7523234bb90fffd26f7d29cdd7648ddd221d46ab Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2544 Tested-by: jenkins Reviewed-by: Stian Skjelstad <stian@nixia.no>
2013-10-10cortex_m: target implementation renames cortex_m3 to cortex_mSpencer Oliver
We changed the actual target name quite a while ago. This changes the actual target function names/defines to also match this change. Change-Id: I4f22fb107636db2279865b45350c9c776e608a75 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1626 Tested-by: jenkins
2013-08-07stlink: add SWO tracing supportAndrey Yurovsky
Enable reading the SWO trace output via STLinkv2 dongles that support it. This adds an optional initialization parameter "trace" with which the user specifies a destination file where SWO trace output is appended as it comes in as well as the trace module's source clock rate. STLink will be configured for a 2MHz SWO data rate (STLink's highest supported rate) if the source clock is > 2MHz, otherwise the source clock is used as the data rate directly. For example: trace swo.log 168000000 If "trace" is specified with a usable file path, the stlink_usb driver will attempt to configure and read SWO trace data as follows: - on _run(), the target's TPI and TMI are configured and the STLinkv2 is told to enable tracing. Only generic ARM TPI and TMI registers are configured, any MCU-specific settings (ex: pin routing) are the responsibility of the target firmware. The configuration applied is based on the STLinkv2's capabilities (UART emulation). - on _v2_get_status(), the trace data (if any) is fetched from the STLink after the target status is checked and the target is found to be running. - on _halt(), the STLink is told to disable tracing. When fetching trace data, the entire trace frame is written to the output file and that data is flushed. An external tool may be used to parse the trace data into a more human-readable format. Tested on ARM Cortex M4F and M3 MCUs (STM32F407 and STM32L152). Change-Id: Ic3983d46c82ba77010c23b0e18ce7b275d917f12 Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Reviewed-on: http://openocd.zylin.com/1524 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2012-12-23hla: fix watchpoints not being setSpencer Oliver
Watchpoints were not being enabled when the hl adapter target was resumed. This effects both stlink and icdi interfaces. Change-Id: Ia9f8a9415be97a467cd099b63b6bc9f7f37d0c0d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/931 Tested-by: jenkins
2012-11-05cortex_m: fix define formattingSpencer Oliver
Change-Id: Ibdec882b2afc7e16f2361f86715463e030a54964 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/963 Tested-by: jenkins
2012-11-05rtos: Add FPU detection to ChibiOS/RTMatthias Blaicher
The stacking of ChibiOS/RT depends on the usage of an FPU. If the FPU is enabled the FPU registers are also saved on context switch. This patch adds automatic detection of FPU for armv7m targets. Note: With this patch, openocd will only output an error message warning that the FPU is enabled. For further FPU support, the correct stacking information also needs to be added. Change-Id: I0984cbd9180f247ba2fa610e74a6413cc54239ea Signed-off-by: Matthias Blaicher <matthias@blaicher.com> Reviewed-on: http://openocd.zylin.com/961 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-03-14stm32: determine all cpu types and use common examineMathias K
This patch determine all cpu types and not only the cortex M3 and the stm32 target use the common target examine function from the cortex_m sources. Change-Id: If689dd994b3855284b927fc4b206f420cf32b6c7 Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/511 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-02-06build: cleanup src/target directorySpencer Oliver
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-03Make cortex_m3 functions public accessible.Mathias K
Change this functions to make it accessible for other target implementations. Change-Id: Ib41fc793cfb4de5439af026c2e8b52e7a9507c85 Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/278 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-11-01target: rename cortex_m3.[ch] to cortex_m.[ch]Spencer Oliver
This rename is in preparation for cortex_m4 support. Change-Id: Ic08c298ec6ed2aabc2c39db67191f68b3a51f550 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/147 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-16 23:32:20 +0000