aboutsummaryrefslogtreecommitdiff
path: root/src/target/armv8.c
AgeCommit message (Collapse)Author
2018-07-13target: armv8: Avoid semihosting segfault on haltAndreas Färber
Avoid a NULL pointer dereference when halting an aarch64 core. Change-Id: I333d40475ab26e2f0dca5c27302a5fa4d817a12f Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/4593 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-07-13Add ARM v8 AArch64 semihosting supportOmair Javaid
This patch implements semihosting support for AArch64. This picks code from previously submitted AArch64 semihosting support patch and rebases on top of reworked semihosting code. Tested in AArch64 mode on a Lemaker Hikey Board with NewLib and GDB. Change-Id: I228a38f1de24f79e49ba99d8514d822a28c2950b Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4537 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-06-04Rework/update ARM semihostingLiviu Ionescu
In 2016, ARM released the second edition of the semihosting specs ("Semihosting for AArch32 and AArch64"), adding support for 64-bits. To ease the reuse of the semihosting logic for other platforms (like RISC-V), the semihosting code was isolated from the ARM target and updated to the latest specs. The new code is already in use since January (in GNU MCU Eclipse OpenOCD) and no problems were reported, neither for ARM nor for RISC-V targets, after more than 7K downloads. The 2 new files were formatted with uncrustify. Change-Id: Ie84dbd86a547323bb8a5d24eab68fc7dad013d96 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4518 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10armv8: valgrind memleak fixesMatthias Welwarsky
Various fixes for memory leaks, adds a target cleanup for aarch64 and ARM CTI objects. Change-Id: I2267f0894df655fdf73d70c11ed03df0b8f8d07d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4478 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-03-30target: restructure dap supportMatthias Welwarsky
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-27aarch64: add cpsr bitfields to target descriptionMatthias Welwarsky
provide meta information for the cpsr so gdb can display the status flags and not only a hexadecimal number Change-Id: I9d3fb29153780adbea389d7e4175d5e19bddc256 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4460 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-16aarch64: fix debug entry from EL0Matthias Welwarsky
If we enter debug state from EL0, some registers are not accessible. Temporarily move to EL1H and back to gain access. Also, fix armv8_dpm_modeswitch() to not immediately restore the previous state on elevating the privilege level. Change-Id: Ic2a92109230ff4eb6834c00ef544397a5b7ad56a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4461 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-10Support for AArch32 SIMD/Floating-point registersOmair Javaid
This patch adds support for read/write of SIMD and floating-point register in AArch32 mode. This patch is tested using Raspberry Pi3 halted in AArch32 mode with FP/SIMD enabled. Software need to make sure floating-point and SIMD unit is enabled. Change-Id: I2b3b8af02257c6420e5a70c6f4c91f839c1f5ee5 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4446 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-10Support AArch64 SIMD/FP registers read/writeOmair Javaid
This patch adds support in openOCD to read/write AArch64 SIMD/FP registers. This patch depends on a previous patch which adds support to generation of target xml by openOCD with nested architecture defined types. AArch64 SIMD/FP registers assumes various types and to support all types we implement them as architecture defined type aarch64v which in turn consists of various architecture defined types. This is compatible with AArch64-FPU target xml in GDB. Please refer to binutils-gdb/gdb/features/aarch64-fpu.xml Change-Id: I7ffb0c21b3c2e08f13720b765408b30aab2a9808 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4373 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-16aarch64: simplify mode and state handlingMatthias Welwarsky
Aarch32 and Aarch64 modes don't conflict in CPSR, no need to deconflict ARMv7-M profile modes either. Change-Id: I4c437dfa657f9e8a1da3687bc9f21435384b7881 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4144 Tested-by: jenkins Reviewed-by: Yao Qi <qiyaoltc@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2017-05-02Fix compile failure on MacOSXMatthias Welwarsky
MacOSX tool chain defines __unused in "sys/cdefs.h", causing a collision. Remove the local define to avoid polluting the compilers internal symbol namespace. Change-Id: I16370c4518e6aeec482dd689e7db80628f846ee3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4118 Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2017-02-24armv8: spelling and formatting updatesMatthias Welwarsky
small changes to correct code formatting and spelling of some log messages. Change-Id: I645e675f8f9f4731b0271ddc55f64e8cf56ec1db Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3994 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24armv8: factor out generic bit set/clr for debug registersMatthias Welwarsky
introduce armv8_set_dbgreg_bits() function to make register bit-field modifications easier to read. Change-Id: I6b06f66262587fd301d848c9e0645e8327653de7 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3989 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24armv8: load aarch32 register through aarch64 equivalentMatthias Welwarsky
The aarch32 register cache is only a separate view of the aarch64 registers. Load aarch32 registers through their aarch64 equivalents. Change-Id: I3e932dfb782f03d73d30d942b24db340a5749e47 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3988 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: reduce debug output to improve legibilityMatthias Welwarsky
Suppress some very verbose LOG_DEBUG's that are not really useful any more. Change-Id: I67f10ba9510a9e34a027f378f4b62b8901ddc8a4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3984 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-10aarch64: remove unused struct componentsMatthias Welwarsky
remove unused register index array from armv8_mode_data[] Change-Id: I686c20eeb3da413f5e9ef6058e31ce939741afb4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: enlarge value buffer of arm_reg to store 64 bitMatthias Welwarsky
struct arm_reg::value[] must be 8 byte to hold a 64bit register value. Change-Id: If253e90731d0ee855eafd9d7b63b91f84630cc7c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: enable aarch32 debugging with arm gdbMatthias Welwarsky
When a PE is in Aarch32 state and gdb asks for a target description, provide a register view compatible with the "org.gnu.gdb.arm.core" feature. Only current-mode registers are exported, banked registers are not visible. Change-Id: I99a85d94831cf597fe8cff6a0a1818ce0a33613b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: allow reading TTBR register when halted in EL0Matthias Welwarsky
There's no access to TTBR in EL0. Circumvent by moving the PE to EL1 before reading, and switch back to original mode afterwards. Change-Id: I22891b958d3d7e6fad1cb27183c192d975d63d89 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix mode switchingMatthias Welwarsky
DCPS only allows to enter higher ELs, for lower ELs you need to use DRPS. Also, of course the encoding differs between A64 and T32. Both DCPS and DRPS also clobber DLR and DSPSR, which then need to be restored on resume. Change-Id: Ifa3dcfa94212702e57170bd59fd0bb25495fb6fd Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: register access rewriteMatthias Welwarsky
All register access is now performed through common read/write functions, which delegate the actual register access to the armv8_common object. armv8_common contains function pointers to direct read and write requests to the respective low-level functions for each PE state. The respective read/write functions are selected on debug state entry. At the same time, T32 opcodes are now formatted for ITR in dpmv8_exec_opcode() and the T32_FMTITR macro is removed from global visibility. Change-Id: I9eaef017c7cc9e0c531e693c534901bfdbdb842c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: simplify armv8_read_ttbcrMatthias Welwarsky
Read registers based on current EL instead of PE mode. Change-Id: I05d3219ac1bf8585e9f4f024a7e8599fea0913b6 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: simplify armv8_set_cpsr()Matthias Welwarsky
Translate from cpsr value to "enum arm_mode" by shifting up 4 bits and filling the lowest nibble with 0xF. Change-Id: Ic32186104b0c29578c4f6f99e04840ab88a0017b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: provide virt2phys commandMatthias Welwarsky
Use AT commands to translate virtual to physical addresses based on current MMU configuration. Change-Id: I1bbd7d674c435541b617b17022fa9f7f0f01bdab Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove bogus os_border calculationMatthias Welwarsky
The artificial "os_border" doesn't exist in aarch64 state and is wrong for aarch32 state as well. Remove it. Change-Id: I7c673a1404b03aa78dbd505e115fa3a93f7ca05f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: armv8 cache functions updateMatthias Welwarsky
Update cache identification to match functionality present in armv7a_cache.c Change-Id: I2dc4bee80f5a22b8728334d40331c183d1406f27 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add basic Aarch32 supportMatthias Welwarsky
Add database for common, equivalent opcodes for Aarch32 and Aarch64 execution states Revisit all functions that access Aarch64 specific registers or use Aarch64 opcodes and rewrite them to act depending on current state of the core. Add core register access functions for Aarch32 state Add function to determine the core execution state without reading DSPSR. Change-Id: I345e9f6d682fb4ba454e4b1d16bb5e1b27570691 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix register listMatthias Welwarsky
According to gdb documentation, a register "cpsr" is expected if aarch64 features are announced. Also, the value buffer must be capable of holding a 64bit value (8 byte, not 4) Change-Id: I7aec4e84fa87eadb26797acd0d16c988b9852616 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove code for AHB-AP supportMatthias Welwarsky
Reduce complexity of memory access functions, anyway there are no ARMv8 platforms that actually contain an AHB-AP at all. while at it, fix virt-to-phys function signatures to expect target_addr_t. Change-Id: I55a369686f42993988b6323e5a77f38de12530a9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix armv8_set_core_reg when destination is cpsrMatthias Welwarsky
When armv8_set_core_reg is used to set the value of the CPSR, also update the internal architecture state. Change-Id: I5f6a2be6fde8d91ec3352d8ba23c4aa90eb02977 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use correct A64 instructions for cache handlingMatthias Welwarsky
Replace A32 MCR with proper A64 MSR opcodes Change-Id: I64a60b17a58a26b199d2d1b2d5d91098e0c8cbd0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: correct display for aarch64 stateMatthias Welwarsky
Aarch64 state has different PSTATE and exception level model. Correct the printout e.g. in poll command. Change-Id: I1820fd1836c7076ae0aa405fa335fd1a14a2e5b3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use symbolic constant for register countMatthias Welwarsky
Aarch64 has 34 registers, but use ARMV8_LAST_REG instead of raw integer constant. Change-Id: I86481899ade74f27fc90eff9f367d444c03e535e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove armv7-a virt-to-phys codeMatthias Welwarsky
Page table layout in aarch64 is very different from armv7-a layout. Remove the incorrect handling, to be replaced correct armv8 code in a later patch Change-Id: I64c728a72a24f9f4177726ccc07a02a8ca0d56ce Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix cache identificationMatthias Welwarsky
Use correct instructions to access CLIDR, CSSELR and CCSIDR. Change-Id: I319b96c03a44fdb59fcb18a00f816f6af0261f0a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix reading of translation table registersMatthias Welwarsky
Correctly access and parse aarch64 ttbcr. Change-Id: I1b1652791a6b5200f58033925286292d838e8410 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: introduce dpm extension for ARMv8Matthias Welwarsky
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix reading of MPIDRMatthias Welwarsky
read MPIDR register through correct MSR instruction. Change-Id: I7e2d00c2871191c4168b177a7a809443b0db4c82 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add ARMv8 AARCH64 support filesDavid Ung
Add new AARCH64 target and ARMv8 support files. This is an instantiation from the cortex_a files but modified to support 64bit ARMv8. Not all features are complete, notably breakpts and single stepping are not yet implemented. Currently it lets you halt of the processors, resume, dump cpu registers, read/write memory and getting a stack trace with gdb. > halt invalid mode value encountered 5 target state: halted unrecognized psr mode: 0x5 target halted in ARM state due to debug-request, current mode: UNRECOGNIZED cpsr: 0x600001c5 pc: 0x00093528 MMU: disabled, D-Cache: disabled, I-Cache: disabled > targets TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* cpu0 aarch64 little cpu.dap halted > reg ===== arm v8 registers (0) r0 (/64): 0x00000000FFFFFFED (dirty) (1) r1 (/64): 0x00000000F76E4000 (2) r2 (/64): 0x0000000000000000 (3) r3 (/64): 0x0000000000010000 (4) r4 (/64): 0xFFFFFFC06E2939E1 (5) r5 (/64): 0x0000000000000018 (6) r6 (/64): 0x003A699CFB3C8480 (7) r7 (/64): 0x0000000053555555 (8) r8 (/64): 0x00FFFFFFFFFFFFFF (9) r9 (/64): 0x000000001FFEF992 (10) r10 (/64): 0x0000000000000001 (11) r11 (/64): 0x0000000000000000 (12) r12 (/64): 0x00000000000000F0 (13) r13 (/64): 0x00000000EFDFEAC8 (14) r14 (/64): 0x00000000F6DDA659 (15) r15 (/64): 0x0000000000000000 (16) r16 (/64): 0xFFFFFFC0000F9094 (17) r17 (/64): 0x0000000000000000 (18) r18 (/64): 0x0000000000000000 (19) r19 (/64): 0xFFFFFFC00087C000 (20) r20 (/64): 0x0000000000000002 (21) r21 (/64): 0xFFFFFFC000867C28 (22) r22 (/64): 0xFFFFFFC000916A52 (23) r23 (/64): 0xFFFFFFC00116D8B0 (24) r24 (/64): 0xFFFFFFC000774A0C (25) r25 (/64): 0x000000008007B000 (26) r26 (/64): 0x000000008007D000 (27) r27 (/64): 0xFFFFFFC000080450 (28) r28 (/64): 0x0000004080000000 (29) r29 (/64): 0xFFFFFFC00087FF20 (30) r30 (/64): 0xFFFFFFC000085114 (31) sp (/64): 0xFFFFFFC00087FF20 (32) pc (/64): 0xFFFFFFC000093528 (33) xPSR (/64): 0x00000000600001C5 And from gdb (gdb) bt #0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87 #1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107 #2 0x0000000000000000 in ?? () Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-22 03:39:26 +0000