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path: root/src/target/armv7a_cache.c
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2015-11-30armv7a: fix-up dcache clean and flush functions inner loop patternMatthias Welwarsky
Other cache functions use an updated pattern for the address range loop. Bring dcache clean and flush functions in line. Change-Id: Iccb4a05c49054471033a3403363110cb08245d5b Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3035 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: Update instruction cache after setting a soft breakpointMatthias Welwarsky
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint, to make sure the d-cache is clean and invalid at the breakpoint location down to PoC. Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint again, so that d-cache will pick up the modified code. Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint to memory to make the change visible to the CPU. Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3033 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: correctly handle invalidation of inner data cachesMatthias Welwarsky
D-Cache invalidate is a dangerous operation. It will only work correctly if full cache lines are invalidated. When partial cache lines are invalidated, i.e. the target address range does not start and end at a cache line boundary, cpu data writes outside of the target range will be dropped. This patch adds special treatment for partial cache lines by doing a clean & invalidate on the partial lines before invalidating the rest of the range. Change-Id: I64099ddb058638e990a7eb0ee911b9cc8f6f8901 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3034 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30armv7a: fix debug messages regarding cache on/off stateMatthias Welwarsky
Cache bits are not level specific, remove "l1" from debug message. Also, fix data/instruction mixup in armv7a_l1_i_cache_sanity_check() Change-Id: I259665ffe62c7ada5b4f98d3fd907e93662d4091 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3028 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: rework automatic flush-on-write handlingMatthias Welwarsky
The following changes are implemented: - Clean&Invalidate the VA range to PoC *before* the write takes place - Remove SMP handling since DCCIMVA instruction already maintains SMP coherence. - Remove separate Invalidate step Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3027 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: add d-cache virtual address range flush functionMatthias Welwarsky
This patch adds a function for cleaning & invalidating a virtual address range from the architecture caches down to the point of coherence. Change-Id: I4061ab023a3797fabc967f3a34498034841d52c6 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3026 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: fix handling of inner cachesMatthias Welwarsky
ARMv7 architecture allows up to 7 cache levels that are architecturally visible, as opposed to "system caches", which are outside of the domain defined by ARMv7 and require separate management. This patch enables detection and identification of caches at all levels. It also implements a new "flush-all" function that cleans & invalidates all cache levels to the "Point of Coherence". Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3024 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: remove special l2x flush-all and cache-info handlersMatthias Welwarsky
This patch is on the path to unified handlers for both inner and outer caches. It removes the special overrides installed when an outer cache is configured. Change-Id: I747f2762c6c8c76c700341cbf6cf500ff2a51476 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3022 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30add armv7a_cache handlersOleksij Rempel
This patch introduces, new command set and handlers for l1 and l2x caches. Patch set 10 folded the following changes into this one: Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415 If8d87a03281d0f4ad402909998e7834eb4837e79 I0749f129fa74e04f4e9c20d143a744f09ef750d8 Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/2800 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>