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2016-05-24Remove FSF address from GPL noticesMarc Schink
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-02-29arm_disassembler: bugfix, MRRC instruction not recognizedAlexander Kurz
A copy-and-paste error in the arm_disassembler opcode evaluation disabled the recognition of MRRC instructions. According to the arm architecture ref. manual issue E or later, MRRC and MCRR instructions are identified by opcode bits 20-27: MCRR = 0xc4, MRRC = 0xc5. Error found by static code analysis using a semantic pattern to detect duplicated tests xand.cocci, see coccinellery.org Change-Id: Ic41426edb51c6816e11dc3d35ef9382ab34af486 Signed-off-by: Alexander Kurz <akurz@blala.de> Reviewed-on: http://openocd.zylin.com/3363 Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-03-09target/arm_disassembler: add exception related disassemblypierre Kuo
Add ERET/HVC/SMC disassebly decoding flow, below is testing result > mdw 0x5c 4 0x0000005c: e160006e e1400072 e1600073 ee110f10 > arm disassemble 0x5c 4 0x0000005c 0xe160006e ERET 0x00000060 0xe1400072 HVC 0x0002 0x00000064 0xe1600073 SMC 0x0003 0x00000068 0xee110f10 MRC p15, 0x00, r0, c1, c0, 0x00 > Change-Id: I1beccff885b5b37747edd0b2e9fb2297ce466a00 Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Reviewed-on: http://openocd.zylin.com/2548 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-05update files to correct FSF addressSpencer Oliver
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2012-08-24build: fix clang warningsMartin Nowak
Change-Id: I3c6a63a18034535f0a8c2c62ba8a708f09d7839b Signed-off-by: Martin Nowak <dawg@dawgfoto.de> Reviewed-on: http://openocd.zylin.com/765 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-02-06build: cleanup src/target directorySpencer Oliver
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-04retire ERROR_INVALID_ARGUMENTS and replace with ERROR_COMMAND_SYNTAX_ERRORØyvind Harboe
Change-Id: I6dee51e1fab1944085391f274a343cdb9014c7a4 Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/300 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-11-07disassembly: fix access to undefined memory pointer upon unknown instructionØyvind Harboe
return error message instead. Found by clang. Change-Id: Ica109d077206236a12d007e77cc78061ffd05834 Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/169 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-06-04Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - trivial fixesFreddie Chopin
2010-12-29warnings: use more 'const' for char *Øyvind Harboe
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-01-21Various doc/comment updatesDavid Brownell
Doxygen: don't be needlessly verbose; alphabetically sort members TODO: add random bits; clarify which manuals are referenced ARM disassembler: mention a few opcodes that still aren't handled Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-01-12ARM: bugfix for "movt" disassemblyDavid Brownell
Use the correct bitfield to specify the register whose top halfword gets replaced. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-14ARM: disassemble STM correctlyDavid Brownell
There is no "STMMIDA" instruction. There is however "STMDAMI". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-11ARM: disassembly fixes for LDC/STC/MRRC/MCRRDavid Brownell
Properly detect all of these, including the "2" variants; and bugfix parameter display for LDC and STC. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-08ARM: cygwin complile fixesDavid Brownell
It's as if despite integers being 32-bits, GCC refuses to convert a "uint32_t" to one of them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: cope with stupidheaded compilerDavid Brownell
Some versions of GCC don't understand that if you mask with 0x3 then have cases 0-3, it's not possible for a variable assigned in all those branches to have no value at end-of-case. Feh. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: disassemble two more v6+ instructionsDavid Brownell
The SRS and RFE instructions speed exception entry/exit by making it easy to save and restore PC and SPSR. This handles both ARM and Thumb2 encodings. Fix minor PLD goofage; that "should never reach this point" can't happen, so remove it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03change #include "log.h" to <helper/log.h>Zachary T Welch
Changes from the flat namespace to heirarchical one. Instead of writing: #include "log.h" the following form should be used. #include <helper/log.h> The exception is from .c files in the same directory.
2009-11-16ARM: standard disassembler uses Thumb2 entryDavid Brownell
Tweak "standard" ARM disassembler diagnostics to fail if the target is not "an ARM" (vs. not "an ARMV4/5"), so it makes more sense for cores inheriting this as the "generic" disassembler. Also, to use the Thumb2 entry instead of the original Thumb entry. This makes it work better for both newer cores (which support those added instructions) and for BL and BLX instructions on older cores. (Those instructions are 32-bits, which requires curious state-aware code to go through a 16-bit decode interface...) Plus minor cleanups, notably to have fewer exit paths and to make sure they all return failure codes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-13target_t -> struct targetZachary T Welch
Remove misleading typedef and redundant suffix from struct target.
2009-11-13arm_instruction_t -> struct arm_instructionZachary T Welch
Remove misleading typedef and redundant suffix from struct arm_instruction.
2009-10-27ARM: fix target address when disassembling Thumb BLXNicolas Pitre
A Thumb BLX instruction is branching to ARM code, and therefore the first 2 bits of the target address must be cleared. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-10-13fix detection of PLD instructionsLennert Buytenhek
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-09-08David Brownell <david-b@pacbell.net> oharboe
lean up some loose ends with the ARM disassembler - Add a header comment describing its current state and uses and referencing the now-generally-available V7 arch spec - Support some mode switch instructions: * Thumb to Jazelle (BXJ) * Thumb to ThumbEE (ENTERX) * ThumbEE to Thumb (LEAVEX) - Improve that recent warning fix (and associated whitespace goof) - Declare the rest of the internal code and data "static". A compiler may use this, and it helps clarify the scope of these routines (e.g. what changes to them could affect). git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-31Warning fixduane
git-svn-id: svn://svn.berlios.de/openocd/trunk@2658 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28David Brownell <david-b@pacbell.net> ARM disassembly support for about five ↵oharboe
dozen non-Thumb instructions that were added after ARMv5TE was defined: - ARMv5J "BXJ" (for Java/Jazelle) - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc) Compile-tested. This might not set up the simulator right for the ARMv6 single step support; only BXJ branches though, and docs to support Jazelle branching are non-public (still, sigh). ARMv6 instructions known to be mis-handled by this disassembler include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2 git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-20David Brownell <david-b@pacbell.net>More Thumb2 disassembly:oharboe
ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch GCC will generate the table branch instructions, usually with inlined tables that will confuse this disassembler. LDREX and STREX are not issued by GCC without inline assembly. This means all Thumb2 instructions implemented by Cortex-M3 can now be disassembled. Cortex-A8 cores support more Thumb2 instructions, but most of those aren't yet publicly documented. git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-16Ferdinand Postema <ferdinand@postema.eu> cygwin 32 bit warningoharboe
git-svn-id: svn://svn.berlios.de/openocd/trunk@2581 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-26David Brownell <david-b@pacbell.net> More testcase work:oharboe
A5.3.11 Data processing (shifted register) The usual kinds of problems; the most noteworthy were that the "S"et flags bit was mis-handled in these instructions. --- This is the last patch from a quickie set of tests covering all encodings of the instructions with 32-bit opcodes. There may be some corner cases left, plus the instructions that aren't yet handled, but the Thumb2 disassembler is no longer just "lightly" tested with GCC output ... the new code paths have mostly been verified. git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-26More instruction decoding fixes:oharboe
A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-26David Brownell <david-b@pacbell.net> More fixes from test cases:oharboe
A5.3.8 Load halfword, unallocated memory hints It's mostly the usual sort of bitmasking goofage and getting the width specs right. In one case an older x86 GCC generated bad code unless I structred a conditional differently (sigh). git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-26David Brownell <david-b@pacbell.net> More instruction decoding fixes:oharboe
A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-24David Brownell <david-b@pacbell.net> More instruction decoding fixes based ↵oharboe
on test cases, covering ARMv7-M arch manual: A5.3.1 Data processing (modified immediate) A5.3.3 Data processing (plain binary immediate) A5.3.4 Branches and miscellaneous control and other (immediate) encodings referenced there. Several of these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but there were a few bugs too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-24David Brownell <david-b@pacbell.net> Bugfix some instruction decoding ... ↵oharboe
I've crafted asm files with testcases covering several new encodings in these sections of the ARMv7-M arch manual: A5.3.12 Data processing (register) A5.3.13 Miscellaneous operations A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, and divide The issues were mostly in '12 and '13; some new related 16-bit opcodes had issues too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-24Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few ↵oharboe
checks for (rt == 0xf) even though that case is handled with an early return at the top of the function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2562 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-23David Brownell <david-b@pacbell.net> thumb2 disassembly for Load halfwordoharboe
git-svn-id: svn://svn.berlios.de/openocd/trunk@2561 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-23David Brownell <david-b@pacbell.net> thumb2 disassembly for Load byte, ↵oharboe
memory hints git-svn-id: svn://svn.berlios.de/openocd/trunk@2560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-23David Brownell <david-b@pacbell.net> fix warningsoharboe
git-svn-id: svn://svn.berlios.de/openocd/trunk@2558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-21David Brownell <david-b@pacbell.net>:ntfreak
Minor updates to the Thumb2 disassembly: - Bugfixes: * Distinguish branch from misc via "!=" not "==" * MRS register shift is 8 bits (vs MSR being 16) - Format tweaks: * CPS needed tab (not space) * add commma before some shifts * add space after comma in LDM/STM * use ".W" width spec on various instructions git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
More 32-bit Thumb2 instruction decoding: A5.3.7 Load word git-svn-id: svn://svn.berlios.de/openocd/trunk@2542 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
More 32-bit Thumb2 instruction decoding: A5.3.12 Data processing (register) git-svn-id: svn://svn.berlios.de/openocd/trunk@2541 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
More 32-bit instruction decoding: A5.3.11 Data processing (shifted register) git-svn-id: svn://svn.berlios.de/openocd/trunk@2540 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
More instructions decoded: A5.3.5 Load/store multiple The preferred PUSH/POP syntax is shown when appropriate. git-svn-id: svn://svn.berlios.de/openocd/trunk@2539 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
More instructions decoded: A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, divide The EABI requires *adjacent* register pairs, but the long multiply ops can use any pair of registers; interesting. git-svn-id: svn://svn.berlios.de/openocd/trunk@2538 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
More Thumb2 32-bit opcode support: A5.3.10 Store single data item Byte, word, halfword. Offset, pre-index, post-index. And a "make like you're unprivileged" option when using small immediate offsets. git-svn-id: svn://svn.berlios.de/openocd/trunk@2537 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
Print old-style Thumb NOP instructions as such. (GCC uses "mov r8, r8" instead of the architected NOP which is new in Thumb2.) git-svn-id: svn://svn.berlios.de/openocd/trunk@2536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
Make disassembly of the Thumb load-literal instruction show the address of the literal being loaded (so users can avoid doing that math themselves). Add and use an Align(PC,4) utility. git-svn-id: svn://svn.berlios.de/openocd/trunk@2535 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
Make the Thumb2 disassembler handle more 32-bit instructions: A5.3.3 Data processing (plain binary immediate) These use mostly twelve bit literals, but there are also bitfield and saturated add primitives. git-svn-id: svn://svn.berlios.de/openocd/trunk@2534 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
Make the Thumb2 disassembler handle more 32-bit instructions: A5.3.1 Data processing (modified immediate) My small sample shows GCC likes to use many of these instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15David Brownell <david-b@pacbell.net>:zwelch
Make the Thumb2 disassembler handle a bunch of 32-bit instructions: A5.3.4 Branches and miscellaneous control Note that this shifts some responsabililty out of helper functions, making the code and layout simpler for 32-bit decoders: they only need to know how to format the instruction and its parameters. Also, technical note: with this patch, Thumb1 decoders could now call the Thumb2 decoder if they wanted to get nicer treatment of the exiting 32-bit B/BLX instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2532 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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