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2018-12-12esirisc: support eSi-TraceSteven Stallion
This patch adds support for instruction tracing to eSi-RISC targets. The command interface is borrowed heavily from ETM; eSi-Trace uses a less sophisticated model for tracing, however the setup and usage is similar. This patch also cleans up the command interfaces of the other esirisc command groups and adds additional debugging information to log messages when dealing with CSRs. This patch "finalizes" support for 32-bit eSi-RISC targets. Change-Id: Ia2a9de79a3c7c066240b5212721fb1b7584a9a45 Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4780 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-08armv7a: ARMv7-A MMU toolsMatthias Welwarsky
factor out mmu-related code from armv7a.c, add a 'dump' command for page tables. Change-Id: Ic1ac3c645d7fd097e9d625c7c8302e7065875dd4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4327 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-10-16esirisc: support eSi-RISC targetsSteven Stallion
eSi-RISC is a highly configurable microprocessor architecture for embedded systems provided by EnSilica. This patch adds support for 32-bit targets and also includes an internal flash driver and uC/OS-III RTOS support. This is a non-traditional target and required a number of additional changes to support non-linear register numbers and the 'p' packet in RTOS support for proper integration into EnSilica's GDB port. Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4660 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-09-10target/mem_ap: generic mem-ap targetMatthias Welwarsky
This pseudo target allows attaching to any access point on the DAP at the MEM-AP level and read and write addresses on the connected bus. For example, one can create a mem_ap target on the APB-AP and read and write registers of debug components directly. This allows many diagnostic and other features be programmed entirely using TCL, without necessity of adding drivers to OpenOCD. Change-Id: I53229ffd68fb0f96fb68be15b0f3a76cc8843c8e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4002 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Leonard Crestez <cdleonard@gmail.com>
2018-07-24Add RISC-V support.Tim Newsome
This supports both 0.11 and 0.13 versions of the debug spec. Support for `-rtos riscv` will come in a separate commit since it was easy to separate out, and is likely to be more controversial. Flash support for the SiFive boards will also come in a later commit. Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4578 Tested-by: jenkins Reviewed-by: Liviu Ionescu <ilg@livius.net> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-06-04Rework/update ARM semihostingLiviu Ionescu
In 2016, ARM released the second edition of the semihosting specs ("Semihosting for AArch32 and AArch64"), adding support for 64-bits. To ease the reuse of the semihosting logic for other platforms (like RISC-V), the semihosting code was isolated from the ARM target and updated to the latest specs. The new code is already in use since January (in GNU MCU Eclipse OpenOCD) and no problems were reported, neither for ARM nor for RISC-V targets, after more than 7K downloads. The 2 new files were formatted with uncrustify. Change-Id: Ie84dbd86a547323bb8a5d24eab68fc7dad013d96 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4518 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30target: restructure dap supportMatthias Welwarsky
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2017-12-07stm8 : new targetAke Rehnman
New STM8 target based mostly on mips4k. Target communication through STLINK/SWIM. No flash driver yet but it is still possible to program flash through load_image command. The usual target debug methods are implemented. Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/3953 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24target: generic ARM CTI function wrapperMatthias Welwarsky
Not specific to ARMv8, the Cross Trigger Interface deserves an independent access wrapper. Change-Id: I84f8faad15ed3515e0fff7f6cc5d1109ef91a869 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3986 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-10aarch64: add basic Aarch32 supportMatthias Welwarsky
Add database for common, equivalent opcodes for Aarch32 and Aarch64 execution states Revisit all functions that access Aarch64 specific registers or use Aarch64 opcodes and rewrite them to act depending on current state of the core. Add core register access functions for Aarch32 state Add function to determine the core execution state without reading DSPSR. Change-Id: I345e9f6d682fb4ba454e4b1d16bb5e1b27570691 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add cache handling functionsMatthias Welwarsky
For now only D-Cache flush (Clean&Invalidate) and I-Cache invalidate are implemented. That's enough for software breakpoints. Change-Id: I8e96d645a230b51e3490403f4564e59ba6a76cf3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: introduce dpm extension for ARMv8Matthias Welwarsky
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add symbolic definitions for armv8 opcodesMatthias Welwarsky
To replace hexadecimal constants with descriptive names and increase flexibility. Change-Id: I6f7b6f045866ed8b9360f54b640ecdb307eebc51 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add ARMv8 AARCH64 support filesDavid Ung
Add new AARCH64 target and ARMv8 support files. This is an instantiation from the cortex_a files but modified to support 64bit ARMv8. Not all features are complete, notably breakpts and single stepping are not yet implemented. Currently it lets you halt of the processors, resume, dump cpu registers, read/write memory and getting a stack trace with gdb. > halt invalid mode value encountered 5 target state: halted unrecognized psr mode: 0x5 target halted in ARM state due to debug-request, current mode: UNRECOGNIZED cpsr: 0x600001c5 pc: 0x00093528 MMU: disabled, D-Cache: disabled, I-Cache: disabled > targets TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* cpu0 aarch64 little cpu.dap halted > reg ===== arm v8 registers (0) r0 (/64): 0x00000000FFFFFFED (dirty) (1) r1 (/64): 0x00000000F76E4000 (2) r2 (/64): 0x0000000000000000 (3) r3 (/64): 0x0000000000010000 (4) r4 (/64): 0xFFFFFFC06E2939E1 (5) r5 (/64): 0x0000000000000018 (6) r6 (/64): 0x003A699CFB3C8480 (7) r7 (/64): 0x0000000053555555 (8) r8 (/64): 0x00FFFFFFFFFFFFFF (9) r9 (/64): 0x000000001FFEF992 (10) r10 (/64): 0x0000000000000001 (11) r11 (/64): 0x0000000000000000 (12) r12 (/64): 0x00000000000000F0 (13) r13 (/64): 0x00000000EFDFEAC8 (14) r14 (/64): 0x00000000F6DDA659 (15) r15 (/64): 0x0000000000000000 (16) r16 (/64): 0xFFFFFFC0000F9094 (17) r17 (/64): 0x0000000000000000 (18) r18 (/64): 0x0000000000000000 (19) r19 (/64): 0xFFFFFFC00087C000 (20) r20 (/64): 0x0000000000000002 (21) r21 (/64): 0xFFFFFFC000867C28 (22) r22 (/64): 0xFFFFFFC000916A52 (23) r23 (/64): 0xFFFFFFC00116D8B0 (24) r24 (/64): 0xFFFFFFC000774A0C (25) r25 (/64): 0x000000008007B000 (26) r26 (/64): 0x000000008007D000 (27) r27 (/64): 0xFFFFFFC000080450 (28) r28 (/64): 0x0000004080000000 (29) r29 (/64): 0xFFFFFFC00087FF20 (30) r30 (/64): 0xFFFFFFC000085114 (31) sp (/64): 0xFFFFFFC00087FF20 (32) pc (/64): 0xFFFFFFC000093528 (33) xPSR (/64): 0x00000000600001C5 And from gdb (gdb) bt #0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87 #1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107 #2 0x0000000000000000 in ?? () Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-12-08Convert to non-recursive makeAndreas Fritiofson
Change-Id: I11f8bc8553957e2ff083c09e72e16881e4d3bb6f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3865 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08xscale: Move debug handler to contrib/loadersAndreas Fritiofson
Avoid special rules to generate array at compile time by shipping the generated file. Convert to Makefile build like the other loaders. Change-Id: I5a05edddcfaff3d395086cd3aa33120f8a7aa9dc Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3864 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-06-23Support for Freescale LS102x SAPEsben Haabendal
The SAP in LS102x SoC's from Freescale is able to read and write to all physical memory locations, independently of CPU cores and DAP. This implementation is 100% based on reverse-engineering of JTAG communication with an LS1021A SAP using a JTAG debugger with SAP support. And as such, this code is for now "works-for-me", pending verification by other OpenOCD users, or even better, actual information from Freescale on the SAP interface. Change-Id: Ibb30945e017894da5c402f9f633fc513bed4e68c Signed-off-by: Esben Haabendal <esben@haabendal.dk> Reviewed-on: http://openocd.zylin.com/3096 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-02-13quark: add Intel Quark mcu D2000 supportIvan De Cesaris
Add support for the Intel Quark mcu D2000 using the new quark_d2xx target. Changes to the lakemont part are needed for the D2000 core and backwards compatible with the X1000 one. Change-Id: I6e1ef5a5d116344942f08e413965abd3945235fa Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com> Reviewed-on: http://openocd.zylin.com/3199 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-30add armv7a_cache handlersOleksij Rempel
This patch introduces, new command set and handlers for l1 and l2x caches. Patch set 10 folded the following changes into this one: Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415 If8d87a03281d0f4ad402909998e7834eb4837e79 I0749f129fa74e04f4e9c20d143a744f09ef750d8 Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/2800 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-03-25drivers/cmsis-dap: port to common SWD frameworkPaul Fertser
Valgrind-tested. Comparison of flashing performance on an FRDM-KL25Z board running mbed CMSIS-DAP variant, 5MHz clock, old driver: wrote 28096 bytes from file demo.elf in 26.833590s (1.023 KiB/s) verified 27264 bytes in 1.754972s (15.171 KiB/s) this implementation: wrote 28096 bytes from file demo.elf in 3.691939s (7.432 KiB/s) verified 27264 bytes in 0.598987s (44.450 KiB/s) Also tested "Keil ULINK-ME CMSIS-DAP" with an STM32F100 target, 5MHz clock, results reading from flash, old driver: dumped 131072 bytes in 98.445305s (1.300 KiB/s) this implementation: dumped 131072 bytes in 8.242686s (15.529 KiB/s) Change-Id: Ic64d3124b1d6cd9dd1016445bb627c71e189ae95 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2356 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-03-25armv7m: add generic trace support (TPIU, ITM, etc.)Paul Fertser
This provides support for various trace-related subsystems in a generic and expandable way. Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2538 Tested-by: jenkins
2014-08-02Fix some problems with the bin2char utilityAndreas Fritiofson
Don't hardcode the type for the array, just output the array initializer so the includer can choose the type and storage class, zero-terminate at will and so on. Change-Id: I6d5e0710eaaba0a218b3eb32f6569177356f4462 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2176 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-08-02Provide od+sed replacement for the bin2char helperPaul Fertser
Using custom build-time tools is always more problematic, especially for cross-compiling. This alternative implementation assumes "od" (IEEE Std 1003.1-2001) and sed are available which should be the case for any reasonably modern system. Change-Id: I0208f475648c78e7dca127ff4bab60d314b2bf53 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2139 Tested-by: jenkins Reviewed-by: Fatih Aşıcı <fatih.asici@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-03-29Add xscale debug helper sources and everything related to distPaul Fertser
GPL requires providing sources for any derived work. I do not see any reason to not include the xscale stuff into release tarballs. Wildcard matching is used because plain directory name matches implicit rule for executables and xscale.c built is errorneously attempted, and directory name with a slash duplicates a directory (xscale/xscale) in dist. Change-Id: Ie0266470dcb97be87a09ba2dda9b3957f7cbc2fa Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1911 Tested-by: jenkins Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-02-11quark_x10xx: add new target quark_x10xxAdrian Burns
Intel Quark X10xx SoC debug support added Lakemont version 1 (LMT1) is the x86 core in Quark X10xx SoC Generic x86 32-bit code is in x86_32_common.c/h Change-Id: If2bf77275cd0277a82558cd9895b4c66155cf368 Signed-off-by: adrian.burns@intel.com Reviewed-on: http://openocd.zylin.com/1829 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-01-09cmsis-dap: add initial cmsis-dap supportSpencer Oliver
This is based on work from: https://github.com/TheShed/OpenOCD-CMSIS-DAP/tree/cmsis-dap Main changes include moving over to using HIDAPI rather than libusb-1.0 and cleaning up to merge into master. Support for reset using srst has also been added. It has been tested on all the mbed boards as well as the Freedom board from Freescale. These boards only implement SWD mode, however JTAG mode has been tested with a Keil ULINK2 and a stm32 target - but requires a lot more work. Change-Id: I96d5ee1993bc9c0526219ab754c5aad3b55d812d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Reviewed-on: http://openocd.zylin.com/1542 Tested-by: jenkins
2013-09-26Add new target type: OpenRISCFranck Jullien
Add support for OpenRISC target. This implementation supports the adv_debug_sys debug unit core. The mohor dbg_if is not supported. Support for mohor TAP core and Altera Virtual JTAG core are also provided. Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72 Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-on: http://openocd.zylin.com/1547 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-05nds32: add new target type nds32_v2, nds32_v3, nds32_v3mHsiangkai Wang
Add target code for Andes targets. Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1259 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-05aice: add Andes AICE supportHsiangkai Wang
Andes AICE uses USB to transfer packets between OpenOCD and AICE. It uses high-level USB commands to control targets instead of using JTAG signals. I define an interface as aice_port_api_s. It contains all basic operations needed by target-dependent code. Change-Id: I117bc4f938fab2732e44c509ea68b30172d6fdb9 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1256 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-23target: add deprecated target name supportSpencer Oliver
This enables us to change the target name without breaking any target scripts. Change-Id: I635f961e573264d3dab2560f3a803ef1986ccfde Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/919 Tested-by: jenkins
2012-03-11flash: retire unused eCos flash driverØyvind Harboe
even the AT91EB40a's flash is covered by CFI and nobody ever submitted any other drivers based on eCos code. It's just possible that this idea was missing documentation and "marketing", but it's in git if somebody wants to resurrect it. Change-Id: I66449aa6e0997301f9d67f28098789bfc891d6e9 Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/502 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-02-16build: fix automake 1.11.2 issuesSpencer Oliver
automake 1.11.2 throws `pkglibdir' is not a legitimate directory for `DATA' if nobase_dist_pkglib_DATA is used. We work around this issue by defining our own location. Change-Id: I3c29e2df0b67e745283c50d358e31699bd60dc74 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/457 Tested-by: jenkins
2012-01-03STM32 ST-LINK target initial releaseMathias K
STM32 ST-LINK target added. Change-Id: Ibe2b7a3c0d5a8cf73d8680d6019adbdb62d68fa2 Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/279 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-11-01target: rename cortex_m3.[ch] to cortex_m.[ch]Spencer Oliver
This rename is in preparation for cortex_m4 support. Change-Id: Ic08c298ec6ed2aabc2c39db67191f68b3a51f550 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/147 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2011-08-17remove white space before TABJie Zhang
2011-08-09Revert "dsp5680xx: disable for now, it generates warnings"Øyvind Harboe
This reverts commit d567df02b9f3e7d2e7e78b3c2907ecad9aa4bbd4.
2011-06-28dsp5680xx: disable for now, it generates warningsØyvind Harboe
Use "git revert <commit>" to revert this commit, then build and repair and post patch to the mailing list. Warnings generated with: nios2-elf-gcc (GCC) 3.4.6 (Altera Nios II 9.1 b222) openocd/src/target/dsp5680xx.c: In function 'eonce_rx_upper_data': openocd/src/target/dsp5680xx.c:252: warning: cast increases required alignment of target type openocd/src/target/dsp5680xx.c: In function 'eonce_rx_lower_data': openocd/src/target/dsp5680xx.c:268: warning: cast increases required alignment of target type openocd/src/target/dsp5680xx.c: In function 'eonce_pc_store': openocd/src/target/dsp5680xx.c:508: warning: dereferencing type-punned pointer will break strict-aliasing rules openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_read': openocd/src/target/dsp5680xx.c:736: warning: cast increases required alignment of target type openocd/src/target/dsp5680xx.c:737: warning: cast increases required alignment of target type openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write_8': openocd/src/target/dsp5680xx.c:823: warning: cast increases required alignment of target type openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write': openocd/src/target/dsp5680xx.c:938: warning: cast increases required alignment of target type openocd/src/target/dsp5680xx.c:941: warning: cast increases required alignment of target type openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_f_wr': openocd/src/target/dsp5680xx.c:1355: warning: cast increases required alignment of target type
2011-06-17build: add missing files to make distSpencer Oliver
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2011-06-17build: add missing files from dist releaseSpencer Oliver
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2011-05-18partial support for 568013 and 568037, target integration.Rodrigo L. Rosa
2011-04-28smp : infra for smp minimum supportMichel Jaouen
2011-03-22cortex_a: rename cortex_a8.c/h to cortex_a.c/hØyvind Harboe
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-03-22cortex a9: merge cortex a9 and a8 codeØyvind Harboe
better to keep this in a single file. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-01-31cortex_a9: add source files for Cortex A9 support.Aaron Carroll
add target and build support for A9 Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
2010-11-18build: add common.mkSpencer Oliver
Rather than specifying common makefile variables move them all to a common.mk. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-11-04arm964e: Add support for ARM946E target.ddraskovic
So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-08-15avr32: work-in-progressOleksandr Tymoshenko
committed so as to ease cooperation and to let it be improved over time. So far it supports: - halt/resume - registers inspection - memory inspection/modification I'm still getting up to speed with OpenOCD internals and AVR32 so code is a little bit messy and I'd appreciate any feedback.
2010-03-16ADIv5 transport support moves to separate filesDavid Brownell
Unclutter arm_adi_v5.c by moving most transport-specific code to a transport-specific files adi_v5_{jtag,swd}.c ... it's not a full cleanup, because of some issues which need to be addressed as part of SWD support (along with implementing the DAP operations on top of SWD transport): - The mess where mem_ap_read_buf_u32() is currently coded to know about JTAG scan chains, and thus needs rewriting before it will work with SWD; - Initialization is still JTAG-specific Also move JTAG_{DP,ACK}_* constants from adi_v5.h to the JTAG file; no other code should care about those values. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-21Packaging fixDavid Brownell
Don't forget to list target/arm_opcodes.h Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-15target: add basic dsp563xx supportmkdorg@users.sourceforge.net
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