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Updates the Kinetis NOR flash support to handle all known block and sector
sizes. Previously only 2kiB sectors were hard-coded, now all four known
combinations non-volatile sector sizes are supported.
The premise of separating Kinetis Program Flash (PFLASH) from FlexNVM is
also introduced. This means each "block" of flash (in Freescale terms) is
treated as a bank in OpenOCD. Correspondingly, the existing board
configuration for the TWR-K60M512 eval system is updated to recognize two
banks instead of one.
A board config for the TWR-K60F120M is also added.
Bank and sector erase and programming has been checked with both of the
mentioned eval boards.
Change-Id: Iae2d10ebf8f548d0a3698df5430bbbe1ccadc58a
Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Reviewed-on: http://openocd.zylin.com/663
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Jan Dakinevich <jan.dakinevich@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Change-Id: Iffacdce9ce90c4ea7e0c8647860a0056b952f387
Signed-off-by: Mirela Tauciuc <mirela.tauciuc@gmail.com>
Reviewed-on: http://openocd.zylin.com/691
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
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Change-Id: Ie260f3c38b648e66958c014658bb6860171a7cc9
Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Reviewed-on: http://openocd.zylin.com/653
Tested-by: jenkins
Reviewed-by: Bill Traynor <wmat@alphatroop.com>
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Use default_flash_blank_check, this will use the much faster
blank_check_memory handler if supported - 15x quicker on stm32f4.
Otherwise it will fall back to using the slower default_flash_mem_blank_check.
Change-Id: Ia231b3e95468c9e92594dbdbe1fa2d69e1506fc3
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/632
Tested-by: jenkins
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Change-Id: Ib2692d8b79e52cd40f429008047494aa7f552984
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/612
Tested-by: jenkins
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
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cfi_spansion_write_block() passes an arm_algorithm struct to
target_run_algorithm() which in turn calls armv7m_start_algorithm()
which expect an armv7m_algorithm struct.
As armv7m_algorithm is bigger than arm_algorithm, when
armv7m_start_algorithm() writes in the struct, it overrun the buffer,
writting junk on the stack, which latter on generates a segfault.
This patch ensure we use a properly sized armv7m_algorithm struct
when the target is an armv7m.
Change-Id: I4ab67c15ae4bb72454414a81b92a4231dcdb2239
Signed-off-by: Aurelien Jacobs <aurel@gnuage.org>
Reviewed-on: http://openocd.zylin.com/623
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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seems 9933fa334de551096674d4044ed7ac2152213e8b introduce a regression
if the target was anything other than armv4_5 or armv7m.
Just check that we have an arm target.
Change-Id: I67c05138e5be2952ee92e9bfa15e1d050844462a
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/615
Tested-by: jenkins
Reviewed-by: Aurelien Jacobs <aurel@gnuage.org>
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check that the cfi driver supports the current target arch.
Change-Id: I8a95908684de67bf1657d1956f2573662a641cc1
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/614
Tested-by: jenkins
Reviewed-by: Aurelien Jacobs <aurel@gnuage.org>
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This makes the code a bit easier to read as arm_algorithm can
refer to other arch's, not just armv4_5.
Change-Id: I78c99d40f34cda04e06f2daee75b48ff40a1d23d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/613
Tested-by: jenkins
Reviewed-by: Aurelien Jacobs <aurel@gnuage.org>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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The stm32f0 parts use a different address then the rest of the family.
Add a function that returns the correct FLASH_SIZE reg depending on variant.
Change-Id: Idb41580f7162f395b347cec034d6b745847326b7
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/601
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Change-Id: Ibe5254704d6cd879a318a82c4f50d9da3c14276c
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/600
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Change-Id: Ib755474aa46f7233495fae1947bc27cd0b2d6b4f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/599
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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Change-Id: Iab0962021e6243d1df3e7c647654a51b4bf50d72
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/578
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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The first available devkits for the at91sam3x8h had the ES device populated.
The ES device had an error in the CIDR, specifically in the last byte of
which the upper 3 bits identifies the chip family - cortex-m3, arm7tdmi etc.
The problem was fixed on the ES2 devices - Thanks to Pat Hickey for giving me
the heads-up.
Change-Id: I13dd7fbe0cffaf76f948188c9459dc3cf4435570
Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-on: http://openocd.zylin.com/575
Tested-by: jenkins
Reviewed-by: Jim Norris <u17263@att.net>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Atmel introduced 6 new Cortex-M4 processors on 2011-10-26
SAM4S16C - 1024KB flash LQFP100/BGA100
SAM4S16B - 1024KB flash LQFP64/QFN64
SAM4S16A - 1024KB flash LQFP48/QFN48
SAM4S8C - 512KB flash LQFP100/BGA100
SAM4S8B - 512KB flash LQFP64/QFN64
SAM4S8A - 512KB flash LQFP48/QFN48
The SAM4S processors still suffer from the "6 waitstates needed
to program device" errata.
Other relevant changes are:
1. Address of flash memory starts at 0x400000.
2. EWP (Erase page and write page) only works for the first two 8KB "sectors"
3. Because of the EWP not working for all the sectors, normal page writes have
to be used. The default_flash_blank_check is used to check if lockregions
should be erased.
4. The EA (Erase All) command takes 7.3s to complete. (Previous timeout was
500 ms)
5. There are 128 lockable regions of 8KB each.
Implemented default blank checking, and page erase for load_image scenarios.
This is to compensate for the EWP flash commands only working on the
first 2 8KB sectors.
Change-Id: I7c5a52b177f7849a107611fd0f635fc416cfb724
Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-on: http://openocd.zylin.com/528
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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The value returned from target_write_buffer is still ignored.
Change-Id: Icb49d4d1313a5e4f7df68d3f122a5f81cfa0604a
Signed-off-by: Linus Tolke <linus@tigris.org>
Reviewed-on: http://openocd.zylin.com/596
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
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The target address for the partial data needs to be bumped past the
full page data. Otherwise, the partial data overwrites the start of
the flash block.
Change-Id: I1246b2fa8acbdb8193edcf7029309f11d1c6069c
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/555
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
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Add swd_init_reset and swd_add_reset.
Add adapter_assert_reset and adapter_deassert_reset, and call them instead
of JTAG reset functions.
Change-Id: Ib2551c6fbb45513e0ae0dc331cfe3ee3f922298a
Signed-off-by: Simon Qian <simonqian.openocd@gmail.com>
Reviewed-on: http://openocd.zylin.com/526
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Change-Id: I496cb745fb1eb5c9159471838013b8d19418f5c0
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/500
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Add a warn message to inform the user that something is wrong
with the flash settings or command parameters.
Change-Id: Ia55868b2abf2a17845e51620b0f29b2809d841c2
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/280
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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This patch fix the slow flash write issue on pflash only devices.
The Family Reference Manual says:
For devices with FlexNVM: FlexRAM
For devices with program flash only: Programming acceleration RAM
So the acceleration RAM is available for the flash section command on
this device.
Change-Id: If6541a23a4457c5ed8858848a145f35cac63138b
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/509
Tested-by: jenkins
Reviewed-by: Tomas Frydrych <tf+openocd@r-finger.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Atmel introduced 7 new Cortex-M3 processors on 2012-02-28
SAM3X4C - 256KB flash
SAM3X4E - 256KB flash
SAM3X8C - 512KB flash
SAM3X8E - 512KB flash
SAM3X8H (Only on dev-kit - not in production...) - 512KB flash
SAM3A4C - 256KB flash
SAM3A8C - 256KB flash
The SAM3X/A processors still suffer from the "6 waitstates needed
to program device" errata.
The CIDR address for the SAM3X/A processors are different from the
other SAM3 processors. Unfortunately, the chip identification register
is not at a constant address across all of the SAM3 series'. As a
consequence, a simple heuristic is used to find where it's
at... If the contents at the first address is zero, then we know
that the second address is where the chip id register is.
We can deduce this because for those SAM's that have the chip id @ 0x400e0940,
the first address, 0x400e0740, is located in the memory map of the Power
Management Controller (PMC). Furthermore, the address is not used by the PMC.
So when read, the memory controller returns zero.
Another interesting change is the flash bank address for flash bank 1.
It is not fixed at 0x00100000 like the Sam3U. Bank 1 of the at91sam3a/x
series starts at 0x00080000 + half the total flash size. Thus for the 256KB
devices Bank 1 is located at 0x000A0000, and for the 512KB devices Bank 1 is
located at 0x000C0000.
The configuration files for the SAM3X/A processors will follow
Change-Id: I6c3a707c00e05d993a2ad1d5a423f23b37ffd553
Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-on: http://openocd.zylin.com/505
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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even the AT91EB40a's flash is covered by CFI and nobody ever submitted
any other drivers based on eCos code. It's just possible that this
idea was missing documentation and "marketing", but it's in git if
somebody wants to resurrect it.
Change-Id: I66449aa6e0997301f9d67f28098789bfc891d6e9
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/502
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
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Change-Id: I163de2c1bd962e7ea9ca6c741c1c62224c210677
Signed-off-by: Szymon Modzelewski <szmodzelewski@gmail.com>
Reviewed-on: http://openocd.zylin.com/486
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Change-Id: Ifde8783b27c64e4a4bbea180cfa2c86f6a9fe49a
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/496
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
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The SUPC (Supply Controller) registers are on different base addresses on different
SAM3 chips:
SAM3U: 0x400e1210
SAM3N: 0x400e1410
SAM3S: 0x400e1410
This creates a problem with the sam3_reg_list array which is const, but would need
to be changed at runtime to account for this variability. As this register is not
used anywhere, it's simplest to just remove it.
Change-Id: I987eb371648d826aa6d5e9de18d38c7bb66d6fca
Signed-off-by: Attila Kinali <attila@kinali.ch>
Reviewed-on: http://openocd.zylin.com/495
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Change-Id: Ie2177487d4315219eb364db360cb7f88d2720783
Signed-off-by: Attila Kinali <attila@kinali.ch>
Reviewed-on: http://openocd.zylin.com/494
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Lock region count and sector sizes did not match datasheet.
(see 6500C-ATARM-8FE11 "SAM3S Series Datasheet", Table 7-1)
Change-Id: Ic511802f96ed03856467a24a6736349205a0576a
Signed-off-by: Attila Kinali <attila@kinali.ch>
Reviewed-on: http://openocd.zylin.com/493
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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The assert introduced in 00c864835149a96b431fc8f31dd89542d88fd383 checks
whether the programming offset equals to page_size of the flash, while it
wants to check whether the offset is a multiple of the page_size.
Change-Id: I794d021951a28c1cc520b5eea5d500f097721b06
Signed-off-by: Attila Kinali <attila@kinali.ch>
Reviewed-on: http://openocd.zylin.com/482
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
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Change-Id: Ieed9de4b078e1ebf659054a758b4f69acdf5b83e
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/466
Tested-by: jenkins
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Currently stm32lx flash driver will remove the readout protection if set
during a probe.
This may not be what the user wants, so let them decide.
Change-Id: I8575e3b339b10a4f7bac57cca9586dcab513d347
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/465
Tested-by: jenkins
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update as per DS61145 rev J
Change-Id: I2b5da84248ff2f44c7ca9d2ed1c52db453714c05
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/461
Tested-by: jenkins
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This enable the stm32f2x flash driver to use the asynchronous
algorithm support.
Speed increase is as follows:
before - wrote 1048576 bytes from file stm32f4x.bin in 30.453804s (33.625 KiB/s)
after - wrote 1048576 bytes from file stm32f4x.bin in 23.679497s (43.244 KiB/s)
This also fixes a bug that was in the old flash loader.
The old loader waited while bit16 of the status reg was 0, the new
loader waits until this bit is 0 as stated in the flash spec.
Bizarrely this bug did not effect programming on any tested parts.
Change-Id: I3efc94d42cbe81283673a8f4203700638080af6e
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/460
Tested-by: jenkins
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This enable the Stellaris flash driver to use the asynchronous
algorithm support.
Speed increase is as follows:
before - wrote 65536 bytes from file test.bin in 5.486040s (11.666 KiB/s)
after - wrote 65536 bytes from file test.bin in 2.274001s (28.144 KiB/s)
Change-Id: I9004c9aadffa1ae3b0cbf908e6549b5b1f794508
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/403
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
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Currently the stm32f1x flash driver uses an asynchronous algorithm
as part of the block flash programming. This greatly speeds up flash
programming as the target is always running.
Moving the async code to the target enable other targets to use this
added functionality.
Change-Id: I8e53f094c2ef7848a7f86ddb9a35b6edbfc8454a
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/402
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
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the value of zero) on success.
Change-Id: Ifb743c1617e2a6071a87c901fae8165969efcdbf
Signed-off-by: Stian Skjelstad <stian@nixia.no>
Reviewed-on: http://openocd.zylin.com/468
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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I used the CPUID instead of adding a new argument to the flash bank command
Fixed Type in comments
Add the failsafe return value in device_id
Change-Id: Ieb5a46fc002b5390a0c81bc8b49f6c687036ae1d
Signed-off-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-on: http://openocd.zylin.com/438
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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The ref manuals for the stm32f2x (RM0033 Rev4) and stm32f4x (RM0090 rev1)
are unclear to the address of the flash size register (F_ID).
According to contacts @ ST this is the correct address, the manuals will be
updated in due coarse.
Change-Id: If9fb83b3100458d17038cf27c2b23355e1dc5a9e
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/448
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: jenkins
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This issue was caused by uncrustify not correctly converting the doxygen
comments.
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Change-Id: Ie6dc3b057a08603b670cb27312e5f0d989426e6c
Reviewed-on: http://openocd.zylin.com/431
Tested-by: jenkins
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Change-Id: Ic299de969ce566282c055ba4dd8b94892c4c4311
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/420
Tested-by: jenkins
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Change-Id: I21bb466a35168cf04743f5baafac9fef50d01707
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/419
Tested-by: jenkins
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Change-Id: I33c32a884095cff139546f760bc8fa6586e8c5b0
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/417
Tested-by: jenkins
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Correct the offset to the read pointer when clearing it on error.
Also restrict the instruction set to armv6-m so the flash driver can be
used on Cortex-M0 parts with the same flash controller.
Change-Id: I380f9dabcc41fb6e4d43a7e02f355e2381913f39
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/399
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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for some reason the following commit was incorrect
769064de4bd8fc59804c37a418b83fcdba6fd36f
Only the Sandstorm and Fury class should write this register.
Change-Id: Ie18f1da6e9b59fb99cca47aa93c7f2fee447ccea
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/400
Tested-by: jenkins
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Signed-off-by: Fujitsu FM3 Application Team <openocd.fseu@de.fujitsu.com>
Change-Id: Iaf0bacfa5438a0213a65a3d60e7d461965a5a1ac
Reviewed-on: http://openocd.zylin.com/249
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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For example, when blocks 2 and 3 were erased, openocd reported "erased blocks 2 to 4". That should be "2 to 3", I think.
Change-Id: Icece63dedd3dd931b70fa73616819a19572e39de
Signed-off-by: Timo Ketola <timo@exertus.fi>
Reviewed-on: http://openocd.zylin.com/385
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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SPAS register (OOB size) is left wrong after reset with respect to 2KiB page NAND chip. That will lead to ECC errors after 'reset halt'.
Change-Id: If5a4685cb8d6be35879453951611ef1059da219c
Signed-off-by: Timo Ketola <timo@exertus.fi>
Reviewed-on: http://openocd.zylin.com/384
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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This patch is based on Erik Ahlén's work on i.MX35 NFC support. Basically it redefines the CCM.RCSR register which is in a different address in i.MX25.
Change-Id: Ia6faf9cb5efae5e564b72ef9a9b7c7f8bfde3ce0
Signed-off-by: Timo Ketola <timo@exertus.fi>
Reviewed-on: http://openocd.zylin.com/383
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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stellaris_set_flash_timing should only be used for Sandstorm and Fury
device classes.
Change-Id: Ib5eff9d954c039f2c5726a8ecc3ee45d1694cfd3
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/389
Tested-by: jenkins
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read the target class during probe and save for later use.
Change-Id: Ib3ad20edc7d206b7f434bdcc6b947e6a5f06dd1f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/388
Tested-by: jenkins
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