aboutsummaryrefslogtreecommitdiff
path: root/src/flash
AgeCommit message (Collapse)Author
2018-06-06psoc5lp: Add EEPROM flash driverAndreas Färber
Tested on CY8CKIT-059. Change-Id: Ib02262e8eebf0df3d29492b8a7daa65b262da580 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3433 Tested-by: jenkins
2018-06-06flash/nor: Add PSoC 5LP flash driverAndreas Färber
Always probe for ECC mode and display ECC sectors if disabled. Non-ECC write is implemented as zeroing the ECC/config bytes. Erasing ECC sectors is ignored, erase-checking takes them into account. Tested with CY8CKIT-059 (CY8C5888), except ECC mode. Change-Id: If63b9ffca7ad8de038be3c086c49712b629ec554 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/3432 Tested-by: jenkins
2018-06-06flash/nor: Add support for TI CC3220SF internal flashEdward Fewell
Added cc3220sf flash driver to support the TI CC3220SF microcontrollers. Implemented flash driver to support the internal flash of the CC3220SF. The implementation does not support the serial flash of the CC32xx family that requires connection over UART, and not via JTAG/SWD debug. Added config files for both CC32xx devices (no flash) and CC3220SF (with flash). Updated to implement comments from code review. Additional updates to handle remaining comments from review. Additional updates per review. Added code to only request aligned writes and full 32-bit words down to flash helper algorithm. Updated for recent changes in OpenOCD flash code. Removed cc32xx.cfg file made obsolete by this patch. Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4319 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-06-05flash/nor/virtual: copy missing fields from master flash_bank structureBohdan Tymkiv
Change-Id: I4ac71ad4b46ed613192310d85eb385b727649a11 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4505 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2018-06-05flash/nor/core: fix double-free crash with 'virtual' flash banksBohdan Tymkiv
flash_bank structure of 'virtual' flash driver is a full copy of the master flash_bank structure including bank->sectors and bank->prot_blocks pointers. These pointers point to memory locations allocated by the master driver and thus master driver is responsible for deallocating them. Do not free bank->sectors and bank->prot_blocks of 'virtual' driver since they were already released by master flash driver. Change-Id: I01f373d4adb3fc79e2724964926b9276442c5c52 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4504 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-30Fix warnings exposed by GCC8Paul Fertser
gcc (GCC) 8.1.0 generates new warnings and thus fails the build. The ARM disassembler warnings actually exposed a bug in SMALW, SMULW and SMUL instructions decoding. Reported by Eimers on IRC. Change-Id: I200c70f75a9e07a1f13a592addc1c5fb37714440 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4526 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-23psoc6: Run flash algorithm asynchronously to improve performanceBohdan Tymkiv
Existing psoc6 driver starts flash algorithm for each Flash row. This is suboptimal from performance point of view, starting/stopping flash algorithm for each row adds significant overhead. This change starts flash algorithm and leaves it running asynchronously while driver performs flash operations. Performance gain is 170...250% depending on probe: flash write_image img_256k.bin | w/o this change | with this change | ----------------------------------|-----------------|------------------| KitProg2/CMSIS-DAP, SWD @ 1 MHz | 4 KiB/s | 10 KiB/s | J-Link Ultra, SWD @ 1 MHz | 17 KiB/s | 31 KiB/s | J-Link Ultra, SWD @ 4 MHz | 33 KiB/s | 57 KiB/s | Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4472 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23flash/nor, contrib/loaders: add stm32 loaders Makefile and generated .incTomas Vanek
Flash loaders refactored to the new style - use generated .inc instead of hexadecimal machine code in the flash driver source. Change-Id: If65a2099589e210f9450819b467d67819fd841fc Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4439 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10flash/nor/at91sam: implement flash bank deallocation for SAM seriesTomas Vanek
Microchip (former Atmel) SAM drivers allocate a struct per chip. at91sam3, at91sam34: Deallocate all chip structs from the list at once, on the first bank deallocation. at91samd and at91sam4l drivers do not handle more than one bank. Convert them to simple driver_priv allocation and use default_flash_free_driver_priv(). Change-Id: I49d7200f38a4568c7e12f306c27d1b1b72646736 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4416 Tested-by: jenkins
2018-04-10flash/nor/kinetis: implement flash bank deallocationTomas Vanek
Change-Id: I8ef80eae646d3b3eb7f6dd42067f8516adc5abef Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4415 Tested-by: jenkins
2018-04-10flash/nor: handle flash write alignment/padding in the infrastructureTomas Vanek
Most of flash drivers have to ensure proper flash write block alignment and padding. As there was no support for it in the flash infrastructure, each driver does it its own way. Sometimes this part of code is not properly tested and contains bugs. flash_write(_unlock) joins all image sections targeted to one flash bank using padded areas as a glue. This solves alignment problems on section boundaries but imposes other problems. Introduce new flash bank parameters write_start_alignment, write_end_alignment and minimal_write_gap. New flash drivers can just properly set these values instead of handling alignment by its own. Adapt infrastructure (namely flash_write_unlock(), handle_flash_fill_command() and handle_flash_write_bank_command()) to prepare write data padded to an alignment required by the flash bank. Rework flash_write_unlock() to discontinue write block when the gap between sections is bigger than minimum specified in minimal_write_gap. minimal_write_gap is set to one sector by default. Change-Id: I4368dd402dfaf51c193bcbf1332cffff092b239b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4399 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-10target, flash: prepare infrastructure for multi-block blank checkTomas Vanek
'flash erase_check' command runs a check algorithm on a target if possible. The algorithm is run repeatedly for each flash sector. Unfortunately every start and stop of the algorithm impose not negligible overhead. In practice it means checking is faster than plain read only for sectors of size approx 4 kByte or bigger. And checking sectors as short as 512 bytes runs approx 4 times slower than plain read. The patch changes API call target_blank_check_memory() and related to take an array of sectors (or arbitrary memory blocks). Changes in target-specific checking routines are kept minimal. They use only the first block from the array and process it by the unchanged algorithm. default_flash_blank_check() routine repeats target_blank_check_memory() until all blocks are checked, so it works with both multi-block and single-block based checkers. Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-06flash/nor/at91samd: Add "nvmuserrow" command.Stefan Arnold
Add option "nvmuserrow" to "at91samd" for changing and reading the register at 0x804000 which represents various fuses. Change-Id: I6382cc4ac15e6b9681e2f30b0ae60397a6289c3b Signed-off-by: Stefan Arnold <sarnold@sh-sw.de> Reviewed-on: http://openocd.zylin.com/4260 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-04nrf51: Add HWID 0x008F againTomas Vanek
HWID originally added in commit 7829f31a6dd61297e97d8e94fe98a1658eac833e was accidentally omited during refactoring in commit 52885d2b538dcd4184aae14cf2706fb97acccbd9 While on it move old ingeneering sample of 51822 to block of 51822 rev 1 Change-Id: Ie9f15563792a27a72e71df6edbcc6b04490370ed Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4437 Tested-by: jenkins
2018-04-04Fix for warnings detected by clang static analyzerMichele Sardo
Fix for potential memory leakage and for unused/unreported return error code Change-Id: Ifb2c95b60637c3a241ad4bf41d1a328c92ccea4b Signed-off-by: Michele Sardo <msmttchr@gmail.com> Reviewed-on: http://openocd.zylin.com/4476 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-04flash/nor: implement flash bank deallocation in drivers with simple allocTomas Vanek
All drivers which simply allocate one driver_priv memory block per each bank now use default_flash_free_driver_priv() Change-Id: I425bf4213c3632f02dbe11ab819c31eda9b2db62 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4417 Tested-by: jenkins Reviewed-by: Liviu Dudau <liviu@dudau.co.uk> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30flash/nor: implement flash bank deallocation on OpenOCD exitTomas Vanek
Change-Id: I8fcf09b2a85b3b68743f5fd68a31edea933b9b17 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4414 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-07Added support for STMicroelectronics BlueNRG-1 and BlueNRG-2 SoCMichele Sardo
Added configuration files and flash loaders. Change-Id: I768eb3626f4e0eadb206bef90a867cc146fe8c75 Signed-off-by: Michele Sardo <msmttchr@gmail.com> Reviewed-on: http://openocd.zylin.com/4226 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-03-03flash/nor/psoc4: fix protection on devices with 256k flashTomas Vanek
Protection read and setting of the second flash macro did not work. Tested on CY8CKIT-046 Change-Id: I67789399ad1e89bbfc23a95547ecca7753130701 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4425 Tested-by: jenkins
2018-03-03flash/nor/psoc4: fix warningsTomas Vanek
Reported by Clang static analyzer. Change-Id: I1118f303f468b6a78ec6cba692762aee565bdf9e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4407 Tested-by: jenkins
2018-03-03flash/nor/core: fix warning in flash_iterate_address_range_innerTomas Vanek
Refactor the code to improve readability. Reported by Clang static analyzer. Change-Id: I671447050e93c6f067917c4456b36ac11abb4663 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4355 Tested-by: jenkins
2018-03-03flash/nor/psoc4: adjust flash size limited by woundingTomas Vanek
All credit goes to Dmitry Grinberg http://dmitry.gr/index.php?r=05.Projects&proj=24.%20PSoC4%20confidential Change-Id: Iae8fd6f11a7f62e8ffe970473688f6fac5a0a261 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4324 Tested-by: jenkins
2018-02-22flash/nor/core: fix Segmentation fault during flash write of bad formed imgTomas Vanek
flash_write_unlock() sorts sections by base address but does not check if they overlap. In case of overlapped sections an item of padding[] array can get negative and padding loop writes out of allocated buffer. How to replicate: cat two copies of an ihex file to one file and try to flash it. Check for overlapped sections and abort write in such case. Change-Id: I43eee7dc290a8d18faa59567b2118b88ad4bedca Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4397 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-02-14efm32: Refactor EFM32 chip family data, add more chipsJonas Norling
Add support for more EFM32/EFR32 Series 1 families. The family IDs come from the DEVICE_FAMILY list in the EFM32GG11 reference manual, which is the most up to date source I could find. Register locations have been checked against SiLab's header files. No datasheets or headers were available for EFR32MG2, EFR32xG14 and EFM32TG11B, so they are just assumed to follow the pattern. EFM32GG11B has the MSC registers on a different address compared to other chips. This commit attempts not to change current behavior when detecting chips. One detail that has changed is that PAGE_SIZE is read before applying the workaround for old Giant and Leopard Gecko revisions, but this is believed to be OK because the register exists but just has an invalid value in it. The manuals disagree on which of 120 and 121 is WG, so this commit leaves it as is. Change-Id: Ia152b0b9e323defc5158cb02d9a6b04a27008f2a Signed-off-by: Jonas Norling <jonas.norling@cyanconnode.com> Reviewed-on: http://openocd.zylin.com/4263 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
2018-02-14Add support for Cypress PSoC6 family of devicesBohdan Tymkiv
* Tested on CY8CKIT-001 kit with PSoC6 daughter board. * Tested with several J-Link adapters (Ultra+, Basic) Change-Id: I0a818c231e5f0b270c7774037b38d23221d59417 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4233 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-14psoc4: update for 4x00BLE, L, M, S and PRoC BLE devicesTomas Vanek
Flash ROM API command PSOC4_CMD_SET_IMO48 is now optional on new devices. Also code tidy up: - improved system ROM call error detection - probe does not require the target to be halted - default_padded_value and erased_value set to 0 - fixed endianess problem in flash write and protection setting - removed fancy chip detection table as it would be updated too often - psoc4 flash_autoerase is now on by default to ease programming psoc4.cfg distinguishes chip family and uses either proprietary acquire function of a KitProg adapter or TEST_MODE workaround to "reset halt" Change-Id: I2c75ec46ed0a95e09274fad70b62d6eed7b9ecdf Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3807 Tested-by: jenkins Reviewed-by: David Girault <david.f.girault@gmail.com>
2018-02-14flash/nor/at91samd: add SAM R30 familyTomas Vanek
Microchip SAM R30 consist of a MCU SAM L21 and a radio. Similarly SAM R21 = SAM D21 + radio. Therefore SAM R devices was incorporated into SAM D21 and L21 device groups. Change-Id: I3448d784cae888070b57c2f504583760ddffc97f Suggested-by: Martin Deicke <martin.deicke@an-solutions.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4282 Tested-by: jenkins
2018-02-04flash/nor/kinetis_ke: fix warning retval set but not usedTomas Vanek
I see no reason for not returning error from target_run_algorithm() to higher level. Reported by Clang static analyzer. Change-Id: Iaaa8b66e487ecae88c0cf4ae2addba63341c032c Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4391 Tested-by: jenkins Reviewed-by: Ivan Meleca <ivan@artekit.eu>
2018-01-30flash: nor: jtagspi: fix jtagspi_read_status() warningPaul Fertser
Clang static analyzer says that in certain cases "Assigned value is garbage or undefined" there. Change-Id: Ib35a4cf7a553ba9461270a0dc4c4b9b205091e73 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4338 Tested-by: jenkins
2018-01-26nor/nrf5: added nrf51822 QFAAH2Daniel Kucera
Change-Id: I59725e098371c63ec3e6aa1d91bfed36b824a182 Signed-off-by: Daniel Kucera <daniel.kucera@gmail.com> Reviewed-on: http://openocd.zylin.com/4334 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-25flash Kinetis: add K27 and K28 devicesTomas Vanek
Tested on FRDM-K28F. Thanks to Thomas Varghese for donating the kit. Change-Id: Idcdd8bcf992acebd19e5335f7f833356500c45dd Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4255 Tested-by: jenkins Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2018-01-25flash Kinetis: make FCF protection more user friendlyTomas Vanek
The Flash Configuration Field on Kinetis devices requires protection because it is located in program flash space (at 0x400) and writing an improper data to it may permanently lock the device. Even an erased flash sector containing FCF engages security lock (not permanent one) on the next reset or power cycle. 'kinetis fcf_source protection' mode was introduced in the change #3562. Flash driver in this mode sets FCF immediately after sector erase to prevent unintentional security lock. To do so the driver needs to know FCF values before flash image data is actually processed. Flash protection bits are available in bank structure, FOPT can be set by 'kinetis fopt' command and securing device by FSEC is not supported. Nevertheless an inexperienced user flashed the device using an image with FCF values different from those set in OpenOCD config and concluded programming did not work as some verify errors showed. This change tries to write maximum possible from image data retaining FCF protection. Check FCF in programmed data and report if some field differs from values set by OpenOCD flash block protection and 'kinetis fopt' command. Warn user about verify errors caused by FCF protection. On devices with ECC flash (K26, K66 and KV5x) it is impossible to change already programmed FCF - it would result in an ECC error. As FCF was written just after erase in 'kinetis fcf_source protection' mode the warning issued during flash write is the only possible action. On non-ECC flash devices use cumulative flash programming to set FCF values requested in programmed image data. Use FSEC from programmed data only if it does not request a secure mode. Device can be secured only in 'kinetis fcf_source write' mode. Use FOPT from programmed data if its value was not configured in OpenOCD config by 'kinetis fopt' command. Change-Id: If65fbbd7700069f57e4ae32234dce371bff93674 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4228 Tested-by: jenkins Reviewed-by: Robert Foss <robert.foss@memcpy.io> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-25flash: nor: stm32l4x: fix warning in probePaul Fertser
Reading options word can fail, so this needs to be handled. Reported by Clang static analyzer. Change-Id: I9754cab9c4446fa2b20d4b44b0e20724d1bc1beb Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4352 Tested-by: jenkins Reviewed-by: Tim "mithro" Ansell <mithro@mithis.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-13jtagspi: new protocol that includes transfer lengthRobert Jordens
This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13XCF (Xilinx platfrom flash) support.barthess
Change-Id: I4ee6db5f0abdb9fd279cc0edd13f71952a9d295d Signed-off-by: Uladzimir Pylinski <barthess@yandex.ru> Reviewed-on: http://openocd.zylin.com/3914 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13flash/startup: make program accept filenames with spaces and other charactersPaul Fertser
This should allow to process any path names excluding those that have curly braces. Change-Id: I87bf9ddede11e2b28d5826878eb1338143f73c03 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4083 Tested-by: jenkins
2018-01-13flash: startup.tcl: do not disable polling when not exitingPaul Fertser
Change-Id: I31b8a8b4519d65d6587207a71eb08dcee8ddd6fd Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4243 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2017-12-12flash/nor/stm32f2x: fix erase on STM32F413/423Tomas Vanek
Theese devices do not have a gap in sector numbering. The driver translates sectors numbers 12 13... to 16 17... as used on dual bank flash devices. Therefore erase of sector 12 and above fails with error 'stm32x device protected' on F413/423. Drop sector number translation for devices without has_large_mem flag. Change-Id: I65531c0dfe02e2fd0f3d68f0615e0926e9901391 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4299 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-12-12flash/nor/stm32f2x: fix protection block size for F767 in dual bank modeTomas Vanek
A protection block comprises two adjacent sectors in dual bank mode. As there are 64 and 128kB sectors joined in blocks 2 and 8, block size should be computed as a sum of sector sizes. Change-Id: Ie915df8cf7ca232c4565d7e0c514c8933e71fdfe Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4271 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-12-06flash: Add new stm32h7x driver supportAlexandre Torgue
Add basic support for: -STM32H7x (Embedded flash 2M) Erase and write tested on stm32h743. Change-Id: Ie8d8786227cdeee39fcf5663167a053ad8dcef4c Signed-off-by: Rémi Prud'homme <remi.prudhomme@st.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-on: http://openocd.zylin.com/4181 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2017-12-06spi: add n25q256 flashRobert Jordens
* 256 MBit SPI flash * https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_l_256_aba_0.pdf spells out the entire zoo of IDs * used e.g. on Xilinx KCU105 Change-Id: I18b19292b4869627adb9071266271962fec68fb4 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4186 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2017-10-23Fix GCC7 warnings about string truncationFreddie Chopin
GCC7 with -Wall warns about possible string truncation with snprint()-type functions with "directive output may be truncated writing 1 byte into a region of size between 0 and 9 [-Werror=format-truncation=]" + "note: ‘snprintf’ output between 5 and 14 bytes into a destination of size 12" (or similar). Fix this by increasing sizes of buffers. See https://gcc.gnu.org/gcc-7/changes.html Change-Id: Ib848f2a56dd658783534158947ae1be7c0e99d45 Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-on: http://openocd.zylin.com/4175 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2017-10-23Fix GCC7 warnings about switch-case fallthroughsFreddie Chopin
GCC7 with -Wextra warns about switch-case blocks which fallthrough with "this statement may fall through [-Werror=implicit-fallthrough=]". This can be fixed by adding "special" comments: "/* fallthrough */". See https://gcc.gnu.org/gcc-7/changes.html Change-Id: Iba0be791dbdd86984489b2d9a0592bb59828da1e Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-on: http://openocd.zylin.com/4174 Tested-by: jenkins
2017-10-03nrf5: Add nRF52832-QFAA supportSlowcoder
Change-Id: Ica9e34e873cac182662b1e32a9b3164dbc0c935f Signed-off-by: Slowcoder <slowcoder@gmail.com> Reviewed-on: http://openocd.zylin.com/4210 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03nrf51: Rename to nrf5Slowcoder
Renaming of all nrf51 NOR flash code to nrf5, as to prepare the code for being able to flash nrf51 and nrf52 chips. The nrf51 command is retained for backwards compatability. "nRF5" is also the name Nordic Semiconductor uses to describe both the nrf51 and nrf52 chips. Change-Id: I5f4e3f1ec780184b28ad44f735a746e68908c502 Signed-off-by: Slowcoder <slowcoder@gmail.com> Reviewed-on: http://openocd.zylin.com/4209 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03nrf51: Refactor device-listSlowcoder
This cleans up the list of supported nrf51 chips considerably. Change-Id: Ic74685657bb72a8703c0a49df4c48c54604ec2a7 Signed-off-by: Slowcoder <slowcoder@gmail.com> Reviewed-on: http://openocd.zylin.com/4208 Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03stm32lx.c: Read IDcode at appropriate address.Uwe Bonnes
Trying to read the L0 idcode at the L1 idcode address 0xE0042000 often resulted in an uncatched error. Reading at the right L0 address 0x40015800 afterwards results in reading 0. So access to the device is denied.. Change-Id: I6de92cf99a5d5d46c72f9ba055613cbc5753a951 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/3883 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03flash: efm32: add support for EFR-familty (e.g. bluegecko)Andrea Merello
This patch adds support for Blue Gecko and Mighty Gecko chips from Silabs. They have different EFM32_MSC_REGBASE and LOCK register offset. Based on the original patch from Andreas Kemnade. Change-Id: I166c14960ced7c880b68083badd1b31372fefabe Cc: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-on: http://openocd.zylin.com/4034 Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com> Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: chrysn <chrysn@fsfe.org>
2017-10-03stm32f2x: Fix left shift of negative valueMarc Schink
Use unsigned constant for left shift operation in order to avoid the following error with GCC >= 6.0: ../src/flash/nor/stm32f2x.c: In function ‘stm32x_handle_unlock_command’: ../src/flash/nor/stm32f2x.c:1324:67: error: left shift of negative value [-Werror=shift-negative-value] stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1 << bank->num_sectors); Change-Id: I0ac082bd0dbb8dc2f61ffff8fdf486ab7962d2e0 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4207 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Anton Fosselius <anton.fosselius@gmail.com> Reviewed-by: Esben Haabendal <esbenhaabendal@gmail.com>
2017-08-10Support for STM32F722, F723, F413 and F423Andreas Bolsch
IDs for STM32F722, F723, F413 and F423 added, handling of PCROP for F722/723 and additional nWPRT bits for F413/423 implemented. The additional protection bit positions for F413/423 conflict with other options bits for the F7xx variants, additionally the last two sectors share a common bit. Protection for F413 and F767/777 now use protection blocks rather sectors for dealing with protections bits. Checking for halted state in 'lock' and 'unlock' removed: When PCROP is activated in F723, halted state is not detected properly, but lock/unlock sequence is required to disable PCROP. Tested with STM32F723E-Disco, STM32F413ZH-Nucleo. Change-Id: Ie6ddab47a9ae8461087d369b4f289b7f9d1e031c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4045 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-22 03:30:13 +0000