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2015-12-29arm_adi_v5: dap_queue_ap_* DAP->AP parameterAndreas Fritiofson
Move the mandatory dap_ap_select() call into the dap_queue_ap_read/write wrapper. This avoids the need for dap_ap_select() and the notion of a "current" AP within target code. Change-Id: I5cde8f3eef2c662f7458be6f3b3dd44ea693bd74 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3164 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Fix dap apsel confusing behaviour.Andreas Fritiofson
Make dap apsel without arguments show current state instead of changing to AP 0. Change-Id: I75ea10e3e1b8a067f2dc417ec6691dc7ceec1af6 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3163 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Remove all cases of "restoring" previous dap_ap_select()Andreas Fritiofson
All AP operations should select the AP to use before calling it so there's no point in restoring the previous value afterwards. The explicit call to dap_ap_select() before all AP operations should be moved into dap_queue_ap_read/write() which then would have to take the AP as an argument instead of the DAP. Change-Id: Icacb0c76ef2a5ac36b4d2f26b52ec01a8850286e Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3156 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29cortex: Set default memaccess_tck only during examineAndreas Fritiofson
It's currently set during target creation but the AP that will be used for the target is not even known. Change-Id: I4502e7eb1fa8d90f746445b8cf8a4c21cb7d519e Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3155 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29adi_v5_jtag: Remove TAR and CSW prints from jtagdp_transaction_endcheckAndreas Fritiofson
The AP for which the TAR/CSW is printed may not be the one that caused the failure. Remove the flawed output entirely. The correct info is printed in mem_ap_read/write anyway. Change-Id: I97580a0662dcf02e80646e45445cdbfc251122d8 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3154 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Remove all mem_ap_sel_* functionsAndreas Fritiofson
All mem_ap_* functions now make sure the SELECT register is updated with the AP number that it's operating on. This shouldn't have to be handled explicitly. Change-Id: Ib193d8930fabb6a25715064355f98258c9580b5d Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3153 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Rename TAR and CSW setters and make them AP-specificAndreas Fritiofson
Change-Id: I0ab66b259e929e6ba826ada9cf8e35614df46410 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3152 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Split ahbap_debugport_initAndreas Fritiofson
This function does two separate things, powering up the DP and setting up a MEM-AP. But the DP needs to be powered before even searching for a MEM-AP to initialize and targets may have multiple MEM-APs that need initializing. Split the function into dap_dp_init() and mem_ap_init() and change all call sites to use the appropriate one. Change-Id: I92f55e09754a93f3f01dd8e5aa1ffdf60c856126 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3151 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Clean up dap info commandAndreas Fritiofson
Reduce use of magic numbers and add AXI type MEM-AP detection. Don't try to call dap_rom_display on a non-existent AP. AP identification is unique per designer, so make sure the JEDEC code matches ARM when interpreting the AP type. Change-Id: I8e86b7de61811382afe99bf15094ab71b43f5fdf Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3150 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Change mem_ap calls to take pointer to AP and not DAPAndreas Fritiofson
Change-Id: I8d3e42056aa5828cb917ca578a54b7d53846a150 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3149 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29cortex_a: Find debug base using the detected APB-AP and not AP 1Andreas Fritiofson
Change-Id: I6b98c3b4486903029e5a0d6d964bd5c48ff55926 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3148 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Convert the AP references from numbers to pointersAndreas Fritiofson
Change the debug_ap and memory_ap fields of the cortex_a target and the debug_ap field of the cortex_m target to be pointers to the struct adiv5_ap instead of AP numbers in some known DAP. This reduces the dependency on the DAP struct in the targets and enables MEM-AP accesses to take the relevant AP as parameter. Change-Id: I39d7b134d78000564b7eec5bff464adf0ef89147 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3147 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29cortex_m: Discover the AP to use, just like Cortex-AAndreas Fritiofson
This required fixing the AP ID parsing in dap_find_ap() to match IHI0031C. The AXI type was added too. Change-Id: I44577a7848df37586e650dce0fb57ac26f5f858c Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3146 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29cortex_a: Call ahbap_debugport_init on the discovered AP and not 0Andreas Fritiofson
Change-Id: I76bb9bd800697776a375ab803402780c3c7bea35 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3145 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Add a back-pointer from an AP to its DAPAndreas Fritiofson
This will make it possible to reference directly the AP used for debug in the target instance and remove the DAP reference. This will in turn enable getting rid of the need to select an "active" AP in the DAP (using dap apsel). Change-Id: I265846a427c714204f4fd3df3cdb75843686c2d0 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3144 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Remove unused is_swd flagAndreas Fritiofson
Not clear what it was supposed to be used for. It probably shouldn't. Change-Id: Ife1d833e59ba80f93876447d752a0ca7e7b57b0f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3143 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29target/arm: Remove usage of struct arm_jtag in ARMv7 targetsAndreas Fritiofson
The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be able to pass a pointer to it to one common JTAG function which anyway only uses the TAP field. Refactor the function to take a TAP directly, remove the legacy struct from cortex instances and store the TAP pointer only in the DAP. Cortex-M makes a call to arm_jtag_setup_connection() with the struct but the function does nothing useful for a Cortex-M target so remove the call. Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3142 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29swd: Remove DAP from parameter listAndreas Fritiofson
Making the SWD driver aware of the DAP that controls it is a layering violation. The only usage for the DAP pointer is to store the number of idle cycles the AP may need to avoid WAITs. Replace the DAP pointer with a cycle count hint instead to avoid future misuse. Change-Id: I3e64e11a43ba2396bd646a4cf8f9bc331805d802 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3141 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-12-29arm_debug: Support multiple APs per DAP and remove DAP from armv7* structsPatrick Stewart
Separate out the values from adiv5_dap that are associated with a specific AP into a new struct, so we can properly support multiple APs. Remove the DAP struct from the armv7* structs, because we can have multiple CPUs per DAP, and we shouldn't have multiple DAP structs. Tidy up a few places where ap_current is used incorrectly. Change-Id: I0c6ef4b49cc86b140366347aaf9b76c07cbab0a8 Signed-off-by: Patrick Stewart <patstew@gmail.com> Reviewed-on: http://openocd.zylin.com/2984 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex_m: Select an AP when accessing the DAPPatrick Stewart
Prepare to support multiple cortex-m cores on one DAP. Uses mem_ap_sel_* functions and removes mem_ap_* functions. Adds a new debug_ap parameter to the cortex_m (currently set to zero as in existing code). Change-Id: I6926029d1e7bf44a42d453d1aff349bda824ba72 Signed-off-by: Patrick Stewart <patstew@gmail.com> Reviewed-on: http://openocd.zylin.com/2983 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29adi_v5: return proper value on timeoutAlamy Liu
ERROR_WAIT is better than ERROR_FAIL in timeout condition. Change-Id: Iefe837f276a9091ce6c18db5947212c449f49d89 Signed-off-by: Alamy Liu <alamy.liu@gmail.com> Reviewed-on: http://openocd.zylin.com/2934 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29adi_v5: Rename AP_REG_* to MEM_AP_REG_* and add LA supportAlamy Liu
This is a TODO in the src/target/arm_adi_v5.h for MEM-AP registers. Some new registers are introduced in ADIv5.2 specification. MEM_AP_REG_MGT (0x20) // Memory Barrier Transfer register MEM_AP_REG_TAR64 (0x08) // Bits[63:32] of Transfer Address MEM_AP_REG_BASE64 (0xF0) // Bits[63:32] of Debug Base Address Refer to 7.5 MEM-AP register summary in IHI0031C: ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 Change-Id: I3bc4296a04c35f5c64f851e5865d3099922613fa Signed-off-by: Alamy Liu <alamy.liu@gmail.com> Reviewed-on: http://openocd.zylin.com/2904 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex-a: Fix "Detected core" number is always '0'Alamy Liu
Problem No matter what target->coreid is, it always shows Detected core 0 dbgbase: ... In dap_lookup_cs_component(), it decreases the core index value to zero in order to find the desired core. The reference to coreidx is necessary considering "a device which has nested ROM tables, with each core described in its own table." (by Paul Fertser). Change-Id: I9b56d45d6edf6639e748a625ab27787f8e5a5776 Signed-off-by: Alamy Liu <alamy.liu@gmail.com> Reviewed-on: http://openocd.zylin.com/2902 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-28jtag: drivers: bcm2835gpio: fix a typo in informational messagePaul Fertser
Change-Id: I70176f9c623e85ba03d8e08992cade232c1bd7fd Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3176 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-18tcl/board: Add Infineon XMC4800 Relax EtherCAT Kit configAndreas Färber
Tested with "J-Link Lite-XMC4200 Rev.1 compiled Oct 14 2015 10:14:50". Derived from xmc4500-relax.cfg. Change-Id: Ia1edf5cb95088ccd34e3b90570d727bbb401cbf5 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3129 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-12-18xmc4xxx: Add XMC4800 supportAndreas Färber
Tested with EES-AA chip revision on Relax EtherCAT Kit. Change-Id: I457f24d242e0674d1f446c03a329efadff754d6a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3132 Tested-by: jenkins Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-12-18xmc4xxx: Make sector sizes constAndreas Färber
They are only used to initialize the flash bank sectors and never modified. Explicitly specify the array length while at it. Cleanup before adding XMC4800 support. Change-Id: I2985b9a9946b67798dbfd47d8b219d93a7ffc3da Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3131 Tested-by: jenkins Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-12-01cortex_a: fix fast-mode memory readsMatthias Welwarsky
cortex_a_read_apb_ab_memory_fast() uses the wrong order of ITR and DSCR writes when setting up the transfer. ARM DDI0406C says in C8.2 regarding "Fast mode" operation to first switch to fast mode and then latch the instruction in ITR. Current implementation first wrote ITR, causing the instruction to be executed immediately, then switched to fast mode without an instruction latched. Repeated reading of DTRTX didn't execute LDC and thus replicated its current content into the whole buffer. This patch uses the following, revised algorithm: 1) switch to non-blocking mode and issue the LDC for the first word 2) if more than one word is to be read: - switch to fast mode - latch the LDC instruction into ITR (it is _not_ executed) - issue (count-1) reads of DTRTX register, each read returns the current content of DTRTX and re-issues the latched instruction -> now the second-to-last word is in the buffer and the LDC for the last word has been issued. 3) wait for the last instruction to complete 4) switch back to non-blocking mode 5) Read DTRTX for the last (or: only) word and put it into the buffer Change-Id: I44f5c585962ffa5af257c3d5a2a802c122b6b1e4 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3122 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30xsvf: output a warning suggesting using SVFPaul Fertser
Change-Id: Iff13019aa96c528268a2be029b4acd65a00a598e Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2907 Tested-by: jenkins
2015-11-30cortex_a: replace cortex_a_check_address functionMatthias Welwarsky
When accessing memory through the ARM core, privilege levels and mmu access permissions observed. Thus it depends on the current mode of the ARM core whether an access is possible or not. the ARM in USR mode can not access memory mapped to a higher privilege level. This means, if the ARM core is halted while executing at PL0, the debugger would be prevented from setting a breakpoint at an address with a higher privilege level, e.g. in the OS kernel. This is not desirable. cortex_a_check_address() tried to work around this by predicting if an access would fail and switched the ARM core to SVC mode. However, the prediction was based on hardcoded address ranges and only worked for Linux and a 3G/1G user/kernel space split. This patch changes the policy to always switch to SVC mode for memory accesses. It introduces two functions cortex_a_prep_memaccess() and cortex_a_post_memaccess() which bracket memory reads and writes. These function encapsulate all actions necessary for preparation and cleanup. Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3119 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: rework mmu manipulationMatthias Welwarsky
when disabling the mmu to access physical addresses, normally the d-cache must be disabled as well. Disabling the d-cache also requires a full clean&invalidate. However, since all memory writes are treated as write- through no-allocate and memory reads do not allocate cache lines, effectively the d-cache state does not change at all. We can therefore save the the d-cache disabling and flushing. This patch also simplifies the function a bit. Change-Id: Ia17c56a28f432156429cd4596107e3652b788e63 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3114 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: force cache and tlb bypass when cpu is in debug stateMatthias Welwarsky
for minimal impact on the hardware state, force all memory accesses to bypass the caches and tlbs. This may actually be the default, but ARM recommends in DDI0406C to set proper default values on debug init. Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3079 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: fix-up dcache clean and flush functions inner loop patternMatthias Welwarsky
Other cache functions use an updated pattern for the address range loop. Bring dcache clean and flush functions in line. Change-Id: Iccb4a05c49054471033a3403363110cb08245d5b Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3035 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: Update instruction cache after setting a soft breakpointMatthias Welwarsky
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint, to make sure the d-cache is clean and invalid at the breakpoint location down to PoC. Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint again, so that d-cache will pick up the modified code. Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint to memory to make the change visible to the CPU. Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3033 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: correctly handle invalidation of inner data cachesMatthias Welwarsky
D-Cache invalidate is a dangerous operation. It will only work correctly if full cache lines are invalidated. When partial cache lines are invalidated, i.e. the target address range does not start and end at a cache line boundary, cpu data writes outside of the target range will be dropped. This patch adds special treatment for partial cache lines by doing a clean & invalidate on the partial lines before invalidating the rest of the range. Change-Id: I64099ddb058638e990a7eb0ee911b9cc8f6f8901 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3034 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30armv7a: fix debug messages regarding cache on/off stateMatthias Welwarsky
Cache bits are not level specific, remove "l1" from debug message. Also, fix data/instruction mixup in armv7a_l1_i_cache_sanity_check() Change-Id: I259665ffe62c7ada5b4f98d3fd907e93662d4091 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3028 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: rework automatic flush-on-write handlingMatthias Welwarsky
The following changes are implemented: - Clean&Invalidate the VA range to PoC *before* the write takes place - Remove SMP handling since DCCIMVA instruction already maintains SMP coherence. - Remove separate Invalidate step Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3027 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: add d-cache virtual address range flush functionMatthias Welwarsky
This patch adds a function for cleaning & invalidating a virtual address range from the architecture caches down to the point of coherence. Change-Id: I4061ab023a3797fabc967f3a34498034841d52c6 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3026 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: remove indirection for cache info handlerMatthias Welwarsky
There's only one function left that handles cache info display, no need any more for a function pointer and runtime initialization. Change-Id: I90b09577f81607917b11f0ab5600a0e2dce223e2 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3025 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: fix handling of inner cachesMatthias Welwarsky
ARMv7 architecture allows up to 7 cache levels that are architecturally visible, as opposed to "system caches", which are outside of the domain defined by ARMv7 and require separate management. This patch enables detection and identification of caches at all levels. It also implements a new "flush-all" function that cleans & invalidates all cache levels to the "Point of Coherence". Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3024 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: remove special l2x flush-all and cache-info handlersMatthias Welwarsky
This patch is on the path to unified handlers for both inner and outer caches. It removes the special overrides installed when an outer cache is configured. Change-Id: I747f2762c6c8c76c700341cbf6cf500ff2a51476 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3022 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30armv7a: rename l2_cache to outer_cacheMatthias Welwarsky
The outer cache is not necessarily at L2 in a system. Rename functions to make that clear. Change-Id: Ia636a4844f50634f2bdf5cdce285febc1a47c11f Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3020 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30armv7a: remove l1 flush all data handlerOleksij Rempel
deprecated by new code. Change-Id: Ie3db627803a6aae38a5287bd3a748a78ab084b7d Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2801 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30add armv7a_cache handlersOleksij Rempel
This patch introduces, new command set and handlers for l1 and l2x caches. Patch set 10 folded the following changes into this one: Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415 If8d87a03281d0f4ad402909998e7834eb4837e79 I0749f129fa74e04f4e9c20d143a744f09ef750d8 Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/2800 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: add cortex_a_[read|write]_memory_ahbOleksij Rempel
Change-Id: I39c457274e1714a8d42233f7fc490fb58f5cb38e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2798 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: add cortex_a_[read|write]_bufferOleksij Rempel
Change-Id: I82011822d913aa7228f5c6262b540156494bedfe Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2797 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: remove cache handlers from cortex_a_write_phys_memoryOleksij Rempel
This was needed for ahb access Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2796 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: remove ahb support for phys_memory accessOleksij Rempel
Change-Id: I5b7c21c16e95cc1a3160e356d6e64f1f8c449e6e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2795 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-27adi_v5: Fix wrong ap valueAlamy Liu
Problem dap->ap_current is register value, not field value. it restores invalid ap when it calls dap_ap_select(dap, ap_old) later. * assume the current ap is 1, dap->ap_current value would be (1 << 24). ap_old = dap->ap_current; <-- ap_old = 1<<24 = 0x1000000. ... dap_ap_select(dap, ap_old); <-- select 0x1000000, not 1. * All AP registers accessing fail afterwards. One of the reproducible case(s): CORE residents in AP >= 1 dap_lookup_cs_component() being used to find PE(*). In most cases, PE would be found in AP==0, hence the problem is hidden. When AP number is 1, dap->ap_current would have the value of 1<<24. Anyone get the AP value with dap->ap_current and resotre it later would select the wrong AP and all accessing later would fail. The ARM Versatile and/or FPGA would have better chance to provide this kind of environment that PE residents in AP>=1. As they have an 'umbrella' system at AP0, and main system at AP>=1. * PE: Processing Element. AKA Core. See ARM Glossary at http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014g/ABCDEFGH.html Fix Use dap_ap_get_select() to get ap value. a. Retrieve current ap value by calling dap_ap_get_select(); src/flash/nor/kinetis.c src/target/arm_adi_v5.c b. The code is correct (dap->ap_current >> 24), but it's better to use dap_ap_get_select() so everything could be synchronized. src/flash/nor/sim3x.c Change-Id: I97b5a13a3fc5506cf287e299c6c35699374de74f Signed-off-by: Alamy Liu <alamy.liu@gmail.com> Reviewed-on: http://openocd.zylin.com/2935 Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-11-26jlink: Retrieve maximum speed from device.Marc Schink
If supported, the maximum transport speed is now retrieved from the device. Change-Id: I614f405ec91cf199c851781785fd26cbd10c37a6 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2955 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-18 01:27:38 +0000