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-rw-r--r--tcl/target/omap2420.cfg7
-rw-r--r--tcl/target/omap3530.cfg9
-rw-r--r--tcl/target/omap5912.cfg9
-rw-r--r--tcl/target/ti_dm355.cfg22
-rw-r--r--tcl/target/ti_dm365.cfg29
-rw-r--r--tcl/target/ti_dm6446.cfg33
6 files changed, 48 insertions, 61 deletions
diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg
index 01557491..866b4a34 100644
--- a/tcl/target/omap2420.cfg
+++ b/tcl/target/omap2420.cfg
@@ -6,11 +6,6 @@ if { [info exists CHIPNAME] } {
} else {
set _CHIPNAME omap2420
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
@@ -46,7 +41,7 @@ jtag newtap $_CHIPNAME jrc -irlen 2 -ircapture 0x1 -irmask 0x3 -expected-id $_JR
# GDB target: the ARM.
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
# scratch: framebuffer, may be initially unavailable in some chips
$_TARGETNAME configure -work-area-phys 0x40210000
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 27e5b007..84460705 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -42,15 +42,20 @@ target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
# FIXME much of this should be in reset event handlers
proc omap3_dbginit { } {
poll off
- reset
sleep 100
jtag tapenable omap3530.dap
targets
# General Cortex A8 debug initialisation
cortex_a8 dbginit
- # Enable DBGU singal for OMAP353x
+ # Enable DBGU signal for OMAP353x
omap3.cpu mww 0x5401d030 0x00002000
poll on
}
+set PRM_RSTCTRL 0x48307250
+
+omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
+omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
+
+
diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg
index fa0fc9e0..30650cfb 100644
--- a/tcl/target/omap5912.cfg
+++ b/tcl/target/omap5912.cfg
@@ -7,13 +7,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME omap5912
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -30,7 +23,7 @@ jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME unknown -irlen 8
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
proc omap5912_reset {} {
#
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 67b3f7a4..2551c3ed 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -6,19 +6,14 @@ if { [info exists CHIPNAME] } {
} else {
set _CHIPNAME dm355
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
# after JTAG reset until ICEpick is used to route them in.
-#set EMU01 "-disable"
+set EMU01 "-disable"
# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
# needing any ICEpick interaction.
-set EMU01 "-enable"
+#set EMU01 "-enable"
source [find target/icepick.cfg]
@@ -33,8 +28,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -44,8 +38,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x07926001
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -55,7 +48,10 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b73b02f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+ "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
@@ -89,7 +85,7 @@ source [find target/davinci.cfg]
# and the ETB memory (4K) are other options, while trace is unused.
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
# and that the work area is used only with a kernel mmu context ...
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 06a52d28..e2d29bd5 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -7,16 +7,15 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME dm365
}
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-#
-# Also note: when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
source [find target/icepick.cfg]
-set EMU01 "-enable"
-#set EMU01 "-disable"
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID ] } {
@@ -24,8 +23,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -35,8 +33,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x0792602f
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -46,8 +43,10 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b83e02f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+ "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index cc23ad44..4dac3d5f 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -7,20 +7,18 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME dm6446
}
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-# Override by setting EMU01 to "-disable".
-#
-# Also note: when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
source [find target/icepick.cfg]
-set EMU01 "-enable"
-#set EMU01 "-disable"
# Subsidiary TAP: unknown ... must enable via ICEpick
-jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable
+jtag newtap $_CHIPNAME unknown -irlen 8 -disable
jtag configure $_CHIPNAME.unknown -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
@@ -35,8 +33,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -46,8 +43,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x07926001
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -57,9 +53,12 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b70002f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+ "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused.
# Little-endian; use the OpenOCD default.
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-20 03:44:44 +0000