aboutsummaryrefslogtreecommitdiff
path: root/tcl/target/ti_dm355.cfg
diff options
context:
space:
mode:
Diffstat (limited to 'tcl/target/ti_dm355.cfg')
-rw-r--r--tcl/target/ti_dm355.cfg16
1 files changed, 8 insertions, 8 deletions
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 2551c3ed..2903e5d8 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -1,10 +1,10 @@
#
-# Texas Instruments DaVinci family: TMS320DM355
+# Texas Instruments DaVinci family: TMS320DM355
#
if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
+ set _CHIPNAME $CHIPNAME
} else {
- set _CHIPNAME dm355
+ set _CHIPNAME dm355
}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
@@ -18,12 +18,12 @@ set EMU01 "-disable"
source [find target/icepick.cfg]
#
-# Also note: when running without RTCK before the PLLs are set up, you
+# Also note: when running without RTCK before the PLLs are set up, you
# may need to slow the JTAG clock down quite a lot (under 2 MHz).
#
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID ] } {
+if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2b900f0f
@@ -33,7 +33,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID ] } {
+if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x07926001
@@ -43,7 +43,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b73b02f
@@ -81,7 +81,7 @@ dict set dm355 uart2 0x01e06000
source [find target/davinci.cfg]
################
-# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
+# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
# and the ETB memory (4K) are other options, while trace is unused.
set _TARGETNAME $_CHIPNAME.arm