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-rw-r--r--tcl/target/str912.cfg6
1 files changed, 3 insertions, 3 deletions
diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 599a254a..38545ac9 100644
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -13,7 +13,7 @@ if { [info exists ENDIAN] } {
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
-jtag_rclk 16
+adapter_khz 16
adapter_nsrst_delay 100
jtag_ntrst_delay 100
@@ -48,11 +48,11 @@ jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BST
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-start { adapter_khz 16 }
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
+ #adapter_khz 3000
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled