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-rw-r--r--tcl/target/omap3530.cfg4
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 0e20852c..f9dcf7cb 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -62,8 +62,8 @@ proc omap3_dbginit {target} {
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
-jtag_rclk 1000
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+adapter_khz 1000
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick