diff options
Diffstat (limited to 'tcl/target/lpc1751.cfg')
-rw-r--r-- | tcl/target/lpc1751.cfg | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tcl/target/lpc1751.cfg b/tcl/target/lpc1751.cfg new file mode 100644 index 00000000..28edddbb --- /dev/null +++ b/tcl/target/lpc1751.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM, +set CHIPNAME lpc1751 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x2000 +set CPUROMSIZE 0x8000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; |