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Diffstat (limited to 'tcl/target/davinci.cfg')
-rw-r--r--tcl/target/davinci.cfg20
1 files changed, 10 insertions, 10 deletions
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index 9e9369dc..859a9253 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -2,7 +2,7 @@
# Utility code for DaVinci-family chips
#
-# davinci_pinmux: assigns PINMUX$reg <== $value
+# davinci_pinmux: assigns PINMUX$reg <== $value
proc davinci_pinmux {soc reg value} {
mww [expr [dict get $soc sysbase] + 4 * $reg] $value
}
@@ -20,13 +20,13 @@ source [find mem_helper.tcl]
#
# PLL version 0x02: tested on dm355
-# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
+# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
proc pll_v02_setup {pll_addr mult config} {
set pll_ctrl_addr [expr $pll_addr + 0x100]
set pll_ctrl [mrw $pll_ctrl_addr]
# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
- # NOTE: this assumes we should clear that bit
+ # NOTE: this assumes we should clear that bit
set pll_ctrl [expr $pll_ctrl & ~0x0100]
mww $pll_ctrl_addr $pll_ctrl
@@ -57,8 +57,8 @@ proc pll_v02_setup {pll_addr mult config} {
set pll_ctrl [expr $pll_ctrl & ~0x0010]
mww $pll_ctrl_addr $pll_ctrl
- # 9 - optional: write prediv, postdiv, and pllm
- # NOTE: for dm355 PLL1, postdiv is controlled via MISC register
+ # 9 - optional: write prediv, postdiv, and pllm
+ # NOTE: for dm355 PLL1, postdiv is controlled via MISC register
mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
if { [dict exists $config prediv] } {
set div [dict get $config prediv]
@@ -71,7 +71,7 @@ proc pll_v02_setup {pll_addr mult config} {
mww [expr $pll_addr + 0x0128] $div
}
- # 10 - optional: set plldiv1, plldiv2, ...
+ # 10 - optional: set plldiv1, plldiv2, ...
# NOTE: this assumes some registers have their just-reset values:
# - PLLSTAT.GOSTAT is clear when we enter
# - ALNCTL has everything set
@@ -162,7 +162,7 @@ proc pll_v03_setup {pll_addr mult config} {
set pll_ctrl [expr $pll_ctrl & ~0x0008]
mww $pll_ctrl_addr $pll_ctrl
- # 9 - optional: write prediv, postdiv, and pllm
+ # 9 - optional: write prediv, postdiv, and pllm
mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff]
if { [dict exists $config prediv] } {
set div [dict get $config prediv]
@@ -181,8 +181,8 @@ proc pll_v03_setup {pll_addr mult config} {
mww $pll_secctrl_addr 0x00400000
mww $pll_secctrl_addr 0x00410000
- # 11 - optional: set plldiv1, plldiv2, ...
- # NOTE: this assumes some registers have their just-reset values:
+ # 11 - optional: set plldiv1, plldiv2, ...
+ # NOTE: this assumes some registers have their just-reset values:
# - PLLSTAT.GOSTAT is clear when we enter
set aln 0
if { [dict exists $config div1] } {
@@ -283,7 +283,7 @@ proc pll_v03_setup {pll_addr mult config} {
mww $pll_ctrl_addr $pll_ctrl
}
-# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
+# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
# modules can be enabled.
# prepare a non-DSP module to be enabled; finish with psc_go