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-rw-r--r--tcl/target/amdm37x.cfg4
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 3121e8fd..ab2ccab1 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -141,7 +141,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
# 16K to be used as a scratchpad for OpenOCD.
@@ -200,7 +200,7 @@ $_TARGETNAME configure -event gdb-attach {
# reset sequence.
proc amdm37x_dbginit {target} {
# General Cortex A8 debug initialisation
- cortex_a8 dbginit
+ cortex_a dbginit
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
# access to the signal appears to be implementation specific. TI does not