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-rw-r--r--src/flash/nor/at91sam3.c43
1 files changed, 43 insertions, 0 deletions
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 01c96241..37b6dd78 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -1414,8 +1414,51 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* else */
/* Bank1 is the boot rom */
/* endif */
+ /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
{
.chipid_cidr = 0x286E0A20,
+ .name = "at91sam3x8h - ES",
+ .total_flash_size = 512 * 1024,
+ .total_sram_size = 96 * 1024,
+ .n_gpnvms = 3,
+ .n_banks = 2,
+ {
+/* .bank[0] = { */
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK0_BASE_AX,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 16,
+ .sector_size = 16384,
+ .page_size = 256,
+ },
+/* .bank[1] = { */
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 1,
+ .base_address = FLASH_BANK1_BASE_512K_AX,
+ .controller_address = 0x400e0c00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 16,
+ .sector_size = 16384,
+ .page_size = 256,
+
+ },
+ },
+ },
+ /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
+ {
+ .chipid_cidr = 0x286E0A60,
.name = "at91sam3x8h",
.total_flash_size = 512 * 1024,
.total_sram_size = 96 * 1024,