diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/jtag/core.c | 33 | ||||
-rw-r--r-- | src/jtag/jtag.h | 33 | ||||
-rw-r--r-- | src/jtag/tcl.c | 18 | ||||
-rw-r--r-- | src/target/arm926ejs.c | 8 | ||||
-rw-r--r-- | src/target/cortex_a8.c | 112 |
5 files changed, 150 insertions, 54 deletions
diff --git a/src/jtag/core.c b/src/jtag/core.c index 6177c1dc..07eec64f 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -61,8 +61,8 @@ static int jtag_error = ERROR_OK; static const char *jtag_event_strings[] = { [JTAG_TRST_ASSERTED] = "TAP reset", + [JTAG_TAP_EVENT_SETUP] = "TAP setup", [JTAG_TAP_EVENT_ENABLE] = "TAP enabled", - [JTAG_TAP_EVENT_POST_RESET] = "TAP post reset", [JTAG_TAP_EVENT_DISABLE] = "TAP disabled", }; @@ -489,7 +489,7 @@ void jtag_add_tlr(void) /* NOTE: order here matches TRST path in jtag_add_reset() */ jtag_call_event_callbacks(JTAG_TRST_ASSERTED); - jtag_notify_reset(); + jtag_notify_event(JTAG_TRST_ASSERTED); } void jtag_add_pathmove(int num_states, const tap_state_t *path) @@ -704,7 +704,7 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst) * sequence must match jtag_add_tlr(). */ jtag_call_event_callbacks(JTAG_TRST_ASSERTED); - jtag_notify_reset(); + jtag_notify_event(JTAG_TRST_ASSERTED); } } } @@ -1068,6 +1068,7 @@ static int jtag_validate_ircapture(void) int total_ir_length = 0; uint8_t *ir_test = NULL; scan_field_t field; + int val; int chain_pos = 0; int retval; @@ -1100,7 +1101,7 @@ static int jtag_validate_ircapture(void) tap = NULL; chain_pos = 0; - int val; + for (;;) { tap = jtag_tap_next_enabled(tap); if (tap == NULL) { @@ -1111,17 +1112,18 @@ static int jtag_validate_ircapture(void) * REVISIT we might be able to verify some MSBs too, using * ircapture/irmask attributes. */ - val = buf_get_u32(ir_test, chain_pos, 2); - if (val != 1) { - char *cbuf = buf_to_str(ir_test, total_ir_length, 16); - - LOG_ERROR("%s: IR capture error; saw 0x%s not 0x..1", - jtag_tap_name(tap), cbuf); + val = buf_get_u32(ir_test, chain_pos, tap->ir_length); + if ((val & 0x3) != 1) { + LOG_ERROR("%s: IR capture error; saw 0x%0*x not 0x..1", + jtag_tap_name(tap), + (tap->ir_length + 7) / tap->ir_length, + val); - free(cbuf); retval = ERROR_JTAG_INIT_FAILED; goto done; } + LOG_DEBUG("%s: IR capture 0x%0*x", jtag_tap_name(tap), + (tap->ir_length + 7) / tap->ir_length, val); chain_pos += tap->ir_length; } @@ -1232,6 +1234,7 @@ static int jtag_init_inner(struct command_context_s *cmd_ctx) { jtag_tap_t *tap; int retval; + bool issue_setup = true; LOG_DEBUG("Init JTAG chain"); @@ -1249,13 +1252,21 @@ static int jtag_init_inner(struct command_context_s *cmd_ctx) if (jtag_examine_chain() != ERROR_OK) { LOG_ERROR("Trying to use configured scan chain anyway..."); + issue_setup = false; } if (jtag_validate_ircapture() != ERROR_OK) { LOG_WARNING("Errors during IR capture, continuing anyway..."); + issue_setup = false; } + if (issue_setup) + jtag_notify_event(JTAG_TAP_EVENT_SETUP); + else + LOG_WARNING("Bypassing JTAG setup events due to errors"); + + return ERROR_OK; } diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h index 938d854b..f255a70e 100644 --- a/src/jtag/jtag.h +++ b/src/jtag/jtag.h @@ -192,23 +192,32 @@ extern unsigned jtag_tap_count(void); /* - * There are three cases when JTAG_TRST_ASSERTED callback is invoked. The - * event is invoked *after* TRST is asserted(or queued rather). It is illegal - * to communicate with the JTAG interface during the callback(as there is - * currently a queue being built). + * - TRST_ASSERTED triggers two sets of callbacks, after operations to + * reset the scan chain -- via TMS+TCK signaling, or deasserting the + * nTRST signal -- are queued: * - * - TMS reset - * - SRST pulls TRST - * - TRST asserted + * + Callbacks in C code fire first, patching internal state + * + Then post-reset event scripts fire ... activating JTAG circuits + * via TCK cycles, exiting SWD mode via TMS sequences, etc * - * TAP activation/deactivation is currently implemented outside the core - * using scripted code that understands the specific router type. + * During those callbacks, scan chain contents have not been validated. + * JTAG operations that address a specific TAP (primarily DR/IR scans) + * must *not* be queued. + * + * - TAP_EVENT_SETUP is reported after TRST_ASSERTED, and after the scan + * chain has been validated. JTAG operations including scans that + * target specific TAPs may be performed. + * + * - TAP_EVENT_ENABLE and TAP_EVENT_DISABLE implement TAP activation and + * deactivation outside the core using scripted code that understands + * the specific JTAG router type. They might be triggered indirectly + * from EVENT_SETUP operations. */ enum jtag_event { JTAG_TRST_ASSERTED, + JTAG_TAP_EVENT_SETUP, JTAG_TAP_EVENT_ENABLE, JTAG_TAP_EVENT_DISABLE, - JTAG_TAP_EVENT_POST_RESET, }; struct jtag_tap_event_action_s @@ -643,8 +652,8 @@ extern void jtag_execute_queue_noclear(void); /// @returns the number of times the scan queue has been flushed int jtag_get_flush_queue_count(void); -/// Notify all TAP's about a TLR reset -void jtag_notify_reset(void); +/// Report Tcl event to all TAPs +void jtag_notify_event(enum jtag_event); /* can be implemented by hw + sw */ diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c index 53c19e1a..212be355 100644 --- a/src/jtag/tcl.c +++ b/src/jtag/tcl.c @@ -41,7 +41,8 @@ #endif static const Jim_Nvp nvp_jtag_tap_event[] = { - { .value = JTAG_TAP_EVENT_POST_RESET, .name = "post-reset" }, + { .value = JTAG_TRST_ASSERTED, .name = "post-reset" }, + { .value = JTAG_TAP_EVENT_SETUP, .name = "setup" }, { .value = JTAG_TAP_EVENT_ENABLE, .name = "tap-enable" }, { .value = JTAG_TAP_EVENT_DISABLE, .name = "tap-disable" }, @@ -373,7 +374,7 @@ static void jtag_tap_handle_event(jtag_tap_t *tap, enum jtag_event e) for (jteap = tap->event_action; jteap != NULL; jteap = jteap->next) { if (jteap->event == e) { - LOG_DEBUG("JTAG tap: %s event: %d (%s) action: %s\n", + LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s", tap->dotted_name, e, Jim_Nvp_value2name_simple(nvp_jtag_tap_event, e)->name, @@ -384,10 +385,12 @@ static void jtag_tap_handle_event(jtag_tap_t *tap, enum jtag_event e) case JTAG_TAP_EVENT_ENABLE: case JTAG_TAP_EVENT_DISABLE: /* NOTE: we currently assume the handlers - * can't fail. That presumes later code - * will be verifying the scan chains ... + * can't fail. Right here is where we should + * really be verifying the scan chains ... */ tap->enabled = (e == JTAG_TAP_EVENT_ENABLE); + LOG_INFO("JTAG tap: %s %s", tap->dotted_name, + tap->enabled ? "enabled" : "disabled"); break; default: break; @@ -586,13 +589,12 @@ static int jim_jtag_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv) } -void jtag_notify_reset(void) +void jtag_notify_event(enum jtag_event event) { jtag_tap_t *tap; + for (tap = jtag_all_taps(); tap; tap = tap->next_tap) - { - jtag_tap_handle_event(tap, JTAG_TAP_EVENT_POST_RESET); - } + jtag_tap_handle_event(tap, event); } diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 8cb5dbe0..3c808021 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -277,7 +277,7 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t return ERROR_OK; } -int arm926ejs_examine_debug_reason(target_t *target) +static int arm926ejs_examine_debug_reason(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -294,7 +294,11 @@ int arm926ejs_examine_debug_reason(target_t *target) switch (debug_reason) { - /* case 0: no debug entry */ + case 0: + LOG_DEBUG("no *NEW* debug entry (?missed one?)"); + /* ... since last restart or debug reset ... */ + target->debug_reason = DBG_REASON_DBGRQ; + break; case 1: LOG_DEBUG("breakpoint from EICE unit 0"); target->debug_reason = DBG_REASON_BREAKPOINT; diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index f6f13cfc..846d90c3 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -67,6 +67,8 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target, uint32_t *value, int regnum); int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum); +int cortex_a8_assert_reset(target_t *target); +int cortex_a8_deassert_reset(target_t *target); target_type_t cortexa8_target = { @@ -81,8 +83,8 @@ target_type_t cortexa8_target = .resume = cortex_a8_resume, .step = cortex_a8_step, - .assert_reset = NULL, - .deassert_reset = NULL, + .assert_reset = cortex_a8_assert_reset, + .deassert_reset = cortex_a8_deassert_reset, .soft_reset_halt = NULL, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, @@ -138,8 +140,13 @@ int cortex_a8_init_debug_access(target_t *target) /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy); - /* Enabling of instruction execution in debug mode is done in debug_entry code */ - + /* Enabling of instruction execution in debug mode is done in debug_entry code */ + + /* Resync breakpoint registers */ + + /* Since this is likley called from init or reset, update targtet state information*/ + cortex_a8_poll(target); + return retval; } @@ -158,8 +165,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) + { + LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); return retval; } + } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode); @@ -169,8 +179,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) + { + LOG_ERROR("Could not read DSCR register"); return retval; } + } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ return retval; @@ -223,11 +236,25 @@ int cortex_a8_write_cp(target_t *target, uint32_t value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) { int retval; + uint32_t dscr; + /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info; swjdp_common_t *swjdp = &armv7a->swjdp_info; + LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value); + + /* Check that DCCRX is not full */ + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (dscr & (1 << DSCR_DTR_RX_FULL)) + { + LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); + /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ + cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); + } + retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_DTRRX, value); /* Move DTRRX to r0 */ @@ -298,12 +325,25 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r { int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; + uint32_t dscr; /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info; swjdp_common_t *swjdp = &armv7a->swjdp_info; + + LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); + /* Check that DCCRX is not full */ + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (dscr & (1 << DSCR_DTR_RX_FULL)) + { + LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); + /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ + cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); + } + if (Rd > 16) return retval; @@ -1188,6 +1228,33 @@ int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin * Cortex-A8 Reset fuctions */ +int cortex_a8_assert_reset(target_t *target) +{ + + LOG_DEBUG(" "); + + /* registers are now invalid */ + armv4_5_invalidate_core_regs(target); + + target->state = TARGET_RESET; + + return ERROR_OK; +} + +int cortex_a8_deassert_reset(target_t *target) +{ + + LOG_DEBUG(" "); + + if (target->reset_halt) + { + int retval; + if ((retval = target_halt(target)) != ERROR_OK) + return retval; + } + + return ERROR_OK; +} /* * Cortex-A8 Memory access @@ -1265,22 +1332,25 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, exit(-1); } - /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ - /* invalidate I-Cache */ - if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + if (target->state == TARGET_HALTED) { - /* Invalidate ICache single entry with MVA, repeat this for all cache - lines in the address range, Cortex-A8 has fixed 64 byte line length */ - /* Invalidate Cache single entry with MVA to PoU */ - for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) - armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */ - } - /* invalidate D-Cache */ - if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - { - /* Invalidate Cache single entry with MVA to PoC */ - for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) - armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */ + /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ + /* invalidate I-Cache */ + if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + { + /* Invalidate ICache single entry with MVA, repeat this for all cache + lines in the address range, Cortex-A8 has fixed 64 byte line length */ + /* Invalidate Cache single entry with MVA to PoU */ + for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) + armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */ + } + /* invalidate D-Cache */ + if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) + { + /* Invalidate Cache single entry with MVA to PoC */ + for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) + armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */ + } } return retval; @@ -1374,7 +1444,7 @@ int cortex_a8_examine(struct target_s *target) uint32_t didr, ctypr, ttypr, cpuid; LOG_DEBUG("TODO"); - + /* Here we shall insert a proper ROM Table scan */ armv7a->debug_base = OMAP3530_DEBUG_BASE; @@ -1451,7 +1521,7 @@ int cortex_a8_examine(struct target_s *target) /* Configure core debug access */ cortex_a8_init_debug_access(target); - + target->type->examined = 1; return retval; |