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-rw-r--r--src/flash/nor/at91sam3.c2
-rw-r--r--src/flash/nor/at91sam4.c6
-rw-r--r--src/flash/nor/atsamv.c2
-rw-r--r--src/flash/nor/efm32.c6
-rw-r--r--src/flash/nor/niietcm4.c2
-rw-r--r--src/flash/nor/sim3x.c4
-rw-r--r--src/jtag/drivers/openjtag.c2
-rw-r--r--src/jtag/drivers/stlink_usb.c2
-rw-r--r--src/rtos/ChibiOS.c4
-rw-r--r--src/rtos/FreeRTOS.c2
-rw-r--r--src/rtos/mqx.c2
-rw-r--r--src/rtos/rtos_standard_stackings.c2
-rw-r--r--src/target/armv7a.c2
-rw-r--r--src/target/cortex_a.c4
-rw-r--r--src/target/cortex_m.c2
15 files changed, 22 insertions, 22 deletions
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 9d119bbf..9782fd82 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -2482,7 +2482,7 @@ static const char *const eproc_names[] = {
_unknown, /* 0 */
"arm946es", /* 1 */
"arm7tdmi", /* 2 */
- "cortex-m3", /* 3 */
+ "Cortex-M3", /* 3 */
"arm920t", /* 4 */
"arm926ejs", /* 5 */
_unknown, /* 6 */
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 88ff6d7a..bcaaaa0f 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -1407,11 +1407,11 @@ static const char *const eproc_names[] = {
_unknown, /* 0 */
"arm946es", /* 1 */
"arm7tdmi", /* 2 */
- "cortex-m3", /* 3 */
+ "Cortex-M3", /* 3 */
"arm920t", /* 4 */
"arm926ejs", /* 5 */
- "cortex-a5", /* 6 */
- "cortex-m4", /* 7 */
+ "Cortex-A5", /* 6 */
+ "Cortex-M4", /* 7 */
_unknown, /* 8 */
_unknown, /* 9 */
_unknown, /* 10 */
diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c
index 08f8bb8b..77fb7e68 100644
--- a/src/flash/nor/atsamv.c
+++ b/src/flash/nor/atsamv.c
@@ -355,7 +355,7 @@ static int samv_probe(struct flash_bank *bank)
uint8_t eproc = (device_id >> 5) & 0x7;
if (eproc != 0) {
- LOG_ERROR("unexpected eproc code: %d was expecting 0 (cortex-m7)", eproc);
+ LOG_ERROR("unexpected eproc code: %d was expecting 0 (Cortex-M7)", eproc);
return ERROR_FAIL;
}
diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index ab543d61..5627a627 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -144,11 +144,11 @@ static int efm32x_read_info(struct flash_bank *bank,
return ret;
if (((cpuid >> 4) & 0xfff) == 0xc23) {
- /* Cortex M3 device */
+ /* Cortex-M3 device */
} else if (((cpuid >> 4) & 0xfff) == 0xc24) {
- /* Cortex M4 device(WONDER GECKO) */
+ /* Cortex-M4 device (WONDER GECKO) */
} else if (((cpuid >> 4) & 0xfff) == 0xc60) {
- /* Cortex M0plus device */
+ /* Cortex-M0+ device */
} else {
LOG_ERROR("Target is not Cortex-Mx Device");
return ERROR_FAIL;
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 9e32c010..ff72ea0f 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -1719,7 +1719,7 @@ static int niietcm4_auto_probe(struct flash_bank *bank)
static int get_niietcm4_info(struct flash_bank *bank, char *buf, int buf_size)
{
struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
- LOG_INFO("\nNIIET Cortex M4F %s\n%s", niietcm4_info->chip_name, niietcm4_info->chip_brief);
+ LOG_INFO("\nNIIET Cortex-M4F %s\n%s", niietcm4_info->chip_name, niietcm4_info->chip_brief);
snprintf(buf, buf_size, " ");
return ERROR_OK;
diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c
index df4e19c2..bb1743e4 100644
--- a/src/flash/nor/sim3x.c
+++ b/src/flash/nor/sim3x.c
@@ -748,7 +748,7 @@ static int sim3x_read_info(struct flash_bank *bank)
}
if (((cpuid >> 4) & 0xfff) != 0xc23) {
- LOG_ERROR("Target is not CortexM3");
+ LOG_ERROR("Target is not Cortex-M3");
return ERROR_FAIL;
}
@@ -1009,7 +1009,7 @@ COMMAND_HANDLER(sim3x_lock)
return ret;
if ((val & CPUID_CHECK_VALUE_MASK) != CPUID_CHECK_VALUE) {
- LOG_ERROR("Target is not ARM CortexM3 or is already locked");
+ LOG_ERROR("Target is not ARM Cortex-M3 or is already locked");
return ERROR_FAIL;
}
} else {
diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c
index 904ab40d..3d14f6d8 100644
--- a/src/jtag/drivers/openjtag.c
+++ b/src/jtag/drivers/openjtag.c
@@ -32,7 +32,7 @@
***************************************************************************/
/***************************************************************************
- * Version 1.0 Tested on a MCBSTM32 board using a Cortex M3 (stm32f103x), *
+ * Version 1.0 Tested on a MCBSTM32 board using a Cortex-M3 (stm32f103x), *
* GDB and Eclipse under Linux (Ubuntu 10.04) *
* *
***************************************************************************/
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index 649368d0..bbd31d87 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -1164,7 +1164,7 @@ static int stlink_usb_step(void *handle)
if (h->jtag_api == STLINK_JTAG_API_V2) {
/* TODO: this emulates the v1 api, it should really use a similar auto mask isr
- * that the cortex-m3 currently does. */
+ * that the Cortex-M3 currently does. */
stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_HALT|C_MASKINTS|C_DEBUGEN);
stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_STEP|C_MASKINTS|C_DEBUGEN);
return stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_HALT|C_DEBUGEN);
diff --git a/src/rtos/ChibiOS.c b/src/rtos/ChibiOS.c
index 84393860..be91be5f 100644
--- a/src/rtos/ChibiOS.c
+++ b/src/rtos/ChibiOS.c
@@ -226,7 +226,7 @@ static int ChibiOS_update_stacking(struct rtos *rtos)
/* Sometimes the stacking can not be determined only by looking at the
* target name but only a runtime.
*
- * For example, this is the case for cortex-m4 targets and ChibiOS which
+ * For example, this is the case for Cortex-M4 targets and ChibiOS which
* only stack the FPU registers if it is enabled during ChibiOS build.
*
* Terminating which stacking is used is target depending.
@@ -248,7 +248,7 @@ static int ChibiOS_update_stacking(struct rtos *rtos)
struct ChibiOS_params *param;
param = (struct ChibiOS_params *) rtos->rtos_specific_params;
- /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4 */
+ /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4 */
struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
if (is_armv7m(armv7m_target)) {
if (armv7m_target->fp_feature == FPv4_SP) {
diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
index 93137733..a58eed13 100644
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -430,7 +430,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, ch
thread_id + param->thread_stack_offset,
stack_ptr);
- /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4F */
+ /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4F */
int cm4_fpu_enabled = 0;
struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
if (is_armv7m(armv7m_target)) {
diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c
index 272658c8..f0f419c6 100644
--- a/src/rtos/mqx.c
+++ b/src/rtos/mqx.c
@@ -109,7 +109,7 @@ static int mqx_valid_address_check(
enum mqx_arch arch_type = ((struct mqx_params *)rtos->rtos_specific_params)->target_arch;
const char * targetname = ((struct mqx_params *)rtos->rtos_specific_params)->target_name;
- /* Cortex M address range */
+ /* Cortex-M address range */
if (arch_type == mqx_arch_cortexm) {
if (
/* code and sram area */
diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c
index 7d72b4e2..32f82a91 100644
--- a/src/rtos/rtos_standard_stackings.c
+++ b/src/rtos/rtos_standard_stackings.c
@@ -182,7 +182,7 @@ int64_t rtos_generic_stack_align8(struct target *target,
stacking, stack_ptr, 8);
}
-/* The Cortex M3 will indicate that an alignment adjustment
+/* The Cortex-M3 will indicate that an alignment adjustment
* has been done on the stack by setting bit 9 of the stacked xPSR
* register. In this case, we can just add an extra 4 bytes to get
* to the program stack. Note that some places in the ARM documentation
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index b9320d14..6dbe10d7 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -177,7 +177,7 @@ done:
return retval;
}
-/* method adapted to cortex A : reused arm v4 v5 method*/
+/* method adapted to Cortex-A : reused ARM v4 v5 method */
int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
{
uint32_t first_lvl_descriptor = 0x0;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index a97e594e..b345dfc0 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -18,7 +18,7 @@
* michel.jaouen@stericsson.com : smp minimum support *
* *
* Copyright (C) Broadcom 2012 *
- * ehunter@broadcom.com : Cortex R4 support *
+ * ehunter@broadcom.com : Cortex-R4 support *
* *
* Copyright (C) 2013 Kamal Dasu *
* kdasu.kdev@gmail.com *
@@ -2664,7 +2664,7 @@ out:
/*
* Cortex-A Memory access
*
- * This is same Cortex M3 but we must also use the correct
+ * This is same Cortex-M3 but we must also use the correct
* ap number for every access.
*/
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 32b46d34..29f0cdd0 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1932,7 +1932,7 @@ int cortex_m_examine(struct target *target)
}
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
- /* test for floating point feature on cortex-m4 */
+ /* test for floating point feature on Cortex-M4 */
if (i == 4) {
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-22 01:53:25 +0000