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Diffstat (limited to 'src/target/arm_disassembler.c')
-rw-r--r-- | src/target/arm_disassembler.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 35c35203..b93df64d 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -1784,8 +1784,12 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode, } /* TODO: deal correctly with dual opcode (prefixed) BL/BLX; - * these are effectively 32-bit instructions even in Thumb1. - * Might be simplest to always use the Thumb2 decoder. + * these are effectively 32-bit instructions even in Thumb1. For + * disassembly, it's simplest to always use the Thumb2 decoder. + * + * But some cores will evidently handle them as two instructions, + * where exceptions may occur between the two. The ETMv3.2+ ID + * register has a bit which exposes this behavior. */ snprintf(instruction->text, 128, |