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Diffstat (limited to 'doc/openocd.texi')
| -rw-r--r-- | doc/openocd.texi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index ae926970..30a2a461 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4059,6 +4059,8 @@ compact Thumb2 instruction set. not a CPU type. It is based on the ARMv5 architecture. @item @code{openrisc} -- this is an OpenRISC 1000 core. The current implementation supports three JTAG TAP cores: +@item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs, +allowing access to physical memory addresses independently of CPU cores. @itemize @minus @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag}) @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf}) |