1 files changed, 4 insertions, 24 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 15965dab..1245df19 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4169,10 +4169,9 @@ the given target with the given @var{name}; this is
 only relevant on boards which have more than one target.
 @end deffn
 
-@section Target CPU Types and Variants
+@section Target CPU Types
 @cindex target type
 @cindex CPU type
-@cindex CPU variant
 
 Each target has a @dfn{CPU type}, as shown in the output of
 the @command{targets} command. You need to specify that type
@@ -4185,20 +4184,13 @@ what core-specific commands may be available
 (@pxref{Architecture and Core Commands}),
 and more.
 
-For some CPU types, OpenOCD also defines @dfn{variants} which
-indicate differences that affect their handling.
-For example, a particular implementation bug might need to be
-worked around in some chip versions.
-
 It's easy to see what target types are supported,
 since there's a command to list them.
-However, there is currently no way to list what target variants
-are supported (other than by reading the OpenOCD source code).
 
 @anchor{targettypes}
 @deffn Command {target types}
 Lists all supported target types.
-At this writing, the supported CPU types and variants are:
+At this writing, the supported CPU types are:
 
 @itemize @bullet
 @item @code{arm11} -- this is a generation of ARMv6 cores
@@ -4218,17 +4210,9 @@ compact Thumb2 instruction set.
 (Support for this is still incomplete.)
 @item @code{fa526} -- resembles arm920 (w/o Thumb)
 @item @code{feroceon} -- resembles arm926
-@item @code{mips_m4k} -- a MIPS core. This supports one variant:
+@item @code{mips_m4k} -- a MIPS core
 @item @code{xscale} -- this is actually an architecture,
 not a CPU type. It is based on the ARMv5 architecture.
-There are several variants defined:
-@itemize @minus
-@item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
-@code{pxa27x} ... instruction register length is 7 bits
-@item @code{pxa250}, @code{pxa255},
-@code{pxa26x} ... instruction register length is 5 bits
-@item @code{pxa3xx} ... instruction register length is 11 bits
-@end itemize
 @item @code{openrisc} -- this is an OpenRISC 1000 core.
 The current implementation supports three JTAG TAP cores:
 @itemize @minus
@@ -4329,7 +4313,6 @@ and in other places the target needs to be identified.
 @item @var{configparams} ... all parameters accepted by
 @command{$target_name configure} are permitted.
 If the target is big-endian, set it here with @code{-endian big}.
-If the variant matters, set it here with @code{-variant}.
 
 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
 @end itemize
@@ -4343,7 +4326,7 @@ using the @command{$target_name cget} command.
 
 @emph{Warning:} changing some of these after setup is dangerous.
 For example, moving a target from one TAP to another;
-and changing its endianness or variant.
+and changing its endianness.
 
 @itemize @bullet
 
@@ -4360,9 +4343,6 @@ Calling this twice with two different event names assigns
 two different handlers, but calling it twice with the
 same event name assigns only one handler.
 
-@item @code{-variant} @var{name} -- specifies a variant of the target,
-which OpenOCD needs to know about.
-
 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
 whether the work area gets backed up; by default,
 @emph{it is not backed up.}