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-rw-r--r--src/target/aarch64.c94
-rw-r--r--src/target/armv8.h31
2 files changed, 68 insertions, 57 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index d06e6684..4097d116 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -796,59 +796,49 @@ static int aarch64_halt(struct target *target)
uint32_t dscr;
struct armv8_common *armv8 = target_to_armv8(target);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0, &dscr);
+ /* enable CTI*/
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0, 1);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0, &dscr);
+ armv8->cti_base + CTI_CTR, 1);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x140, &dscr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x140, 6);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x140, &dscr);
+ armv8->cti_base + CTI_GATE, 3);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa0, &dscr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa0, 5);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa0, &dscr);
-
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa4, &dscr);
- retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa4, 2);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa4, &dscr);
+ armv8->cti_base + CTI_OUTEN0, 1);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x20, &dscr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x20, 4);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x20, &dscr);
+ armv8->cti_base + CTI_OUTEN1, 2);
+ if (retval != ERROR_OK)
+ return retval;
/*
- * enter halting debug mode
+ * add HDE in halting debug mode
*/
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
-# /* STATUS */
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x134, &dscr);
+ retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_DSCR, dscr | DSCR_HDE);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x1c, &dscr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x1c, 1);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x1c, &dscr);
+ armv8->cti_base + CTI_APPPULSE, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->cti_base + CTI_INACK, 1);
+ if (retval != ERROR_OK)
+ return retval;
long long then = timeval_ms();
@@ -857,7 +847,7 @@ static int aarch64_halt(struct target *target)
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- if ((dscr & DSCR_CORE_HALTED) != 0)
+ if ((dscr & DSCRV8_HALT_MASK) != 0)
break;
if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for halt");
@@ -969,23 +959,7 @@ static int aarch64_internal_restart(struct target *target)
LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DSCR, dscr & ~DSCR_ITR_EN);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DRCR, DRCR_RESTART |
- DRCR_CLEAR_EXCEPTIONS);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x10, 1);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x1c, 2);
+ armv8->cti_base + CTI_APPPULSE, 2);
if (retval != ERROR_OK)
return retval;
@@ -995,7 +969,7 @@ static int aarch64_internal_restart(struct target *target)
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- if ((dscr & DSCR_CORE_RESTARTED) != 0)
+ if ((dscr & DSCR_HDE) != 0)
break;
if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for resume");
@@ -1061,11 +1035,11 @@ static int aarch64_resume(struct target *target, int current,
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
- LOG_DEBUG("target resumed at 0x%" PRIu64, addr);
+ LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
- LOG_DEBUG("target debug resumed at 0x%" PRIu64, addr);
+ LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
}
return ERROR_OK;
@@ -2316,6 +2290,12 @@ static int aarch64_examine_first(struct target *target)
} else
armv8->debug_base = target->dbgbase;
+ LOG_DEBUG("Target ctibase is 0x%x", target->ctibase);
+ if (target->ctibase == 0)
+ armv8->cti_base = target->ctibase = armv8->debug_base + 0x1000;
+ else
+ armv8->cti_base = target->ctibase;
+
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_LOCKACCESS, 0xC5ACCE55);
if (retval != ERROR_OK) {
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 41edb991..9c6ccce4 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -130,6 +130,8 @@ struct armv8_common {
/* Core Debug Unit */
struct arm_dpm dpm;
uint32_t debug_base;
+ uint32_t cti_base;
+
struct adiv5_ap *debug_ap;
struct adiv5_ap *memory_ap;
bool memory_ap_available;
@@ -191,6 +193,35 @@ target_to_armv8(struct target *target)
#define CPUV8_DBG_AUTHSTATUS 0xFB8
+/*define CTI(cross trigger interface)*/
+#define CTI_CTR 0x0
+#define CTI_INACK 0x10
+#define CTI_APPSET 0x14
+#define CTI_APPCLEAR 0x18
+#define CTI_APPPULSE 0x1C
+#define CTI_INEN0 0x20
+#define CTI_INEN1 0x24
+#define CTI_INEN2 0x28
+#define CTI_INEN3 0x2C
+#define CTI_INEN4 0x30
+#define CTI_INEN5 0x34
+#define CTI_INEN6 0x38
+#define CTI_INEN7 0x3C
+#define CTI_OUTEN0 0xA0
+#define CTI_OUTEN1 0xA4
+#define CTI_OUTEN2 0xA8
+#define CTI_OUTEN3 0xAC
+#define CTI_OUTEN4 0xB0
+#define CTI_OUTEN5 0xB4
+#define CTI_OUTEN6 0xB8
+#define CTI_OUTEN7 0xBC
+#define CTI_TRIN_STATUS 0x130
+#define CTI_TROUT_STATUS 0x134
+#define CTI_CHIN_STATUS 0x138
+#define CTI_CHOU_STATUS 0x13C
+#define CTI_GATE 0x140
+#define CTI_UNLOCK 0xFB0
+
int armv8_arch_state(struct target *target);
int armv8_identify_cache(struct target *target);
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-23 07:03:01 +0000