diff options
| -rw-r--r-- | tcl/board/digilent_zedboard.cfg | 11 | ||||
| -rw-r--r-- | tcl/target/zynq_7000.cfg | 25 |
2 files changed, 36 insertions, 0 deletions
diff --git a/tcl/board/digilent_zedboard.cfg b/tcl/board/digilent_zedboard.cfg new file mode 100644 index 00000000..08d1a612 --- /dev/null +++ b/tcl/board/digilent_zedboard.cfg @@ -0,0 +1,11 @@ +# +# Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip +# +# http://zedboard.com/product/zedboard +# + +source [find interface/ftdi/digilent_jtag_smt2.cfg] + +reset_config srst_only srst_push_pull + +source [find target/zynq_7000.cfg] diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg new file mode 100644 index 00000000..55156ac3 --- /dev/null +++ b/tcl/target/zynq_7000.cfg @@ -0,0 +1,25 @@ +# +# Xilinx Zynq-7000 All Programmable SoC +# +# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm +# + +set _CHIPNAME zynq +set _TARGETNAME $_CHIPNAME.cpu + +jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \ + -expected-id 0x23727093 \ + -expected-id 0x03727093 + +jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477 + +target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \ + -coreid 0 -dbgbase 0x80090000 +target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \ + -coreid 1 -dbgbase 0x80092000 +target smp ${_TARGETNAME}0 ${_TARGETNAME}1 + +adapter_khz 1000 + +${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit" +${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit" |