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-rw-r--r--NEWS20
-rw-r--r--TODO3
-rw-r--r--doc/openocd.texi28
-rw-r--r--src/jtag/core.c33
-rw-r--r--src/jtag/jtag.h33
-rw-r--r--src/jtag/tcl.c18
-rw-r--r--src/target/arm926ejs.c8
-rw-r--r--src/target/cortex_a8.c112
-rw-r--r--tcl/target/omap2420.cfg7
-rw-r--r--tcl/target/omap3530.cfg9
-rw-r--r--tcl/target/omap5912.cfg9
-rw-r--r--tcl/target/ti_dm355.cfg22
-rw-r--r--tcl/target/ti_dm365.cfg29
-rw-r--r--tcl/target/ti_dm6446.cfg33
14 files changed, 240 insertions, 124 deletions
diff --git a/NEWS b/NEWS
index c39c5ae7..a5a5401d 100644
--- a/NEWS
+++ b/NEWS
@@ -5,27 +5,43 @@ other issues not mentioned here.
JTAG Layer:
FT2232H (high speed USB) support doesn't need separate configuration
+ New reset_config options for SRST gating the JTAG clock (or not)
+ TAP declaration no longer requires ircapture and mask attributes
+ New "post-reset" event handler for TAP-invariant setup code
Target Layer:
New commands for use with Cortex-M3 processors:
"cortex_m3 disassemble" ... Thumb2 disassembly (UAL format)
"cortex_m3 vector_catch" ... traps certain hardware faults
without tying up breakpoint resources
- If you're willing to help debug it: VERY EARLY Cortex-A8 support
+ If you're willing to help debug it
+ VERY EARLY Cortex-A8 and ARMv7A support
+ Updated BeagleBoard.org hardware support
New commands for use with XScale processors: "xscale vector_table"
- ARM11 single stepping support for i.MX31
+ ARM11
+ single stepping support for i.MX31
+ bugfix for missing "arm11" prefix on "arm11 memwrite ..."
+ ETM support
+ Unavailable registers are not listed
Flash Layer:
The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips
+ New lpc2900 driver for NXP LPC2900 chips (ARM968 based)
+ New "last" flag for NOR "flash erase_sector" and "flash protect"
+ The "nand erase N" command now erases all of bank N
Board, Target, and Interface Configuration Scripts:
+ Amontec JTAGkey2 support
Cleanup and additions for the TI/Luminary Stellaris scripts
LPC1768 target (and flash) support
Keil MCB1700 eval board
Samsung s3c2450
Mini2440 board
+ Numeric TAP and Target identifiers now trigger warnings
Documentation:
+ Capture more debugging and setup advice
+ Notes on target source code changes that may help debugging
Build and Release:
diff --git a/TODO b/TODO
index a2ee398b..4e8cb2d1 100644
--- a/TODO
+++ b/TODO
@@ -137,7 +137,7 @@ https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM923EJS:
- reset run/halt/step is not robust; needs testing to map out problems.
- ARM11 improvements (MB?)
- - fix single stepping (reported by ØH). Need to automatically
+ - Single stepping works, but should automatically
use hardware stepping if available.
- hunt down and add timeouts to all infinite loops, e.g. arm11_run_instr_no_data would
lock up in infinite loop if e.g. an "mdh" command tries to read memory from invalid memory location.
@@ -314,3 +314,4 @@ to complete:
/** @file
This file contains the @ref thelist page.
*/
+
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 32797fb3..8156de4d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2428,12 +2428,18 @@ The TAP events currently defined are:
@itemize @bullet
@item @b{post-reset}
@* The TAP has just completed a JTAG reset.
-For the first such handler called, the tap is still
-in the JTAG @sc{reset} state.
+The tap may still be in the JTAG @sc{reset} state.
+Handlers for these events might perform initialization sequences
+such as issuing TCK cycles, TMS sequences to ensure
+exit from the ARM SWD mode, and more.
+
Because the scan chain has not yet been verified, handlers for these events
@emph{should not issue commands which scan the JTAG IR or DR registers}
of any particular target.
@b{NOTE:} As this is written (September 2009), nothing prevents such access.
+@item @b{setup}
+@* The scan chain has been reset and verified.
+This handler may enable TAPs as needed.
@item @b{tap-disable}
@* The TAP needs to be disabled. This handler should
implement @command{jtag tapdisable}
@@ -2450,7 +2456,7 @@ contents to be accurate), you might:
@example
jtag configure CHIP.jrc -event post-reset @{
- echo "Reset done"
+ echo "JTAG Reset done"
... non-scan jtag operations to be done after reset
@}
@end example
@@ -2493,20 +2499,30 @@ does include a kind of JTAG router functionality.
In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
shown below, and is implemented using TAP event handlers.
So for example, when defining a TAP for a CPU connected to
-a JTAG router, you should define TAP event handlers using
+a JTAG router, your @file{target.cfg} file
+should define TAP event handlers using
code that looks something like this:
@example
jtag configure CHIP.cpu -event tap-enable @{
- echo "Enabling CPU TAP"
... jtag operations using CHIP.jrc
@}
jtag configure CHIP.cpu -event tap-disable @{
- echo "Disabling CPU TAP"
... jtag operations using CHIP.jrc
@}
@end example
+Then you might want that CPU's TAP enabled almost all the time:
+
+@example
+jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
+@end example
+
+Note how that particular setup event handler declaration
+uses quotes to evaluate @code{$CHIP} when the event is configured.
+Using brackets @{ @} would cause it to be evaluated later,
+at runtime, when it might have a different value.
+
@deffn Command {jtag tapdisable} dotted.name
If necessary, disables the tap
by sending it a @option{tap-disable} event.
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 6177c1dc..07eec64f 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -61,8 +61,8 @@ static int jtag_error = ERROR_OK;
static const char *jtag_event_strings[] =
{
[JTAG_TRST_ASSERTED] = "TAP reset",
+ [JTAG_TAP_EVENT_SETUP] = "TAP setup",
[JTAG_TAP_EVENT_ENABLE] = "TAP enabled",
- [JTAG_TAP_EVENT_POST_RESET] = "TAP post reset",
[JTAG_TAP_EVENT_DISABLE] = "TAP disabled",
};
@@ -489,7 +489,7 @@ void jtag_add_tlr(void)
/* NOTE: order here matches TRST path in jtag_add_reset() */
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
- jtag_notify_reset();
+ jtag_notify_event(JTAG_TRST_ASSERTED);
}
void jtag_add_pathmove(int num_states, const tap_state_t *path)
@@ -704,7 +704,7 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
* sequence must match jtag_add_tlr().
*/
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
- jtag_notify_reset();
+ jtag_notify_event(JTAG_TRST_ASSERTED);
}
}
}
@@ -1068,6 +1068,7 @@ static int jtag_validate_ircapture(void)
int total_ir_length = 0;
uint8_t *ir_test = NULL;
scan_field_t field;
+ int val;
int chain_pos = 0;
int retval;
@@ -1100,7 +1101,7 @@ static int jtag_validate_ircapture(void)
tap = NULL;
chain_pos = 0;
- int val;
+
for (;;) {
tap = jtag_tap_next_enabled(tap);
if (tap == NULL) {
@@ -1111,17 +1112,18 @@ static int jtag_validate_ircapture(void)
* REVISIT we might be able to verify some MSBs too, using
* ircapture/irmask attributes.
*/
- val = buf_get_u32(ir_test, chain_pos, 2);
- if (val != 1) {
- char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
-
- LOG_ERROR("%s: IR capture error; saw 0x%s not 0x..1",
- jtag_tap_name(tap), cbuf);
+ val = buf_get_u32(ir_test, chain_pos, tap->ir_length);
+ if ((val & 0x3) != 1) {
+ LOG_ERROR("%s: IR capture error; saw 0x%0*x not 0x..1",
+ jtag_tap_name(tap),
+ (tap->ir_length + 7) / tap->ir_length,
+ val);
- free(cbuf);
retval = ERROR_JTAG_INIT_FAILED;
goto done;
}
+ LOG_DEBUG("%s: IR capture 0x%0*x", jtag_tap_name(tap),
+ (tap->ir_length + 7) / tap->ir_length, val);
chain_pos += tap->ir_length;
}
@@ -1232,6 +1234,7 @@ static int jtag_init_inner(struct command_context_s *cmd_ctx)
{
jtag_tap_t *tap;
int retval;
+ bool issue_setup = true;
LOG_DEBUG("Init JTAG chain");
@@ -1249,13 +1252,21 @@ static int jtag_init_inner(struct command_context_s *cmd_ctx)
if (jtag_examine_chain() != ERROR_OK)
{
LOG_ERROR("Trying to use configured scan chain anyway...");
+ issue_setup = false;
}
if (jtag_validate_ircapture() != ERROR_OK)
{
LOG_WARNING("Errors during IR capture, continuing anyway...");
+ issue_setup = false;
}
+ if (issue_setup)
+ jtag_notify_event(JTAG_TAP_EVENT_SETUP);
+ else
+ LOG_WARNING("Bypassing JTAG setup events due to errors");
+
+
return ERROR_OK;
}
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 938d854b..f255a70e 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -192,23 +192,32 @@ extern unsigned jtag_tap_count(void);
/*
- * There are three cases when JTAG_TRST_ASSERTED callback is invoked. The
- * event is invoked *after* TRST is asserted(or queued rather). It is illegal
- * to communicate with the JTAG interface during the callback(as there is
- * currently a queue being built).
+ * - TRST_ASSERTED triggers two sets of callbacks, after operations to
+ * reset the scan chain -- via TMS+TCK signaling, or deasserting the
+ * nTRST signal -- are queued:
*
- * - TMS reset
- * - SRST pulls TRST
- * - TRST asserted
+ * + Callbacks in C code fire first, patching internal state
+ * + Then post-reset event scripts fire ... activating JTAG circuits
+ * via TCK cycles, exiting SWD mode via TMS sequences, etc
*
- * TAP activation/deactivation is currently implemented outside the core
- * using scripted code that understands the specific router type.
+ * During those callbacks, scan chain contents have not been validated.
+ * JTAG operations that address a specific TAP (primarily DR/IR scans)
+ * must *not* be queued.
+ *
+ * - TAP_EVENT_SETUP is reported after TRST_ASSERTED, and after the scan
+ * chain has been validated. JTAG operations including scans that
+ * target specific TAPs may be performed.
+ *
+ * - TAP_EVENT_ENABLE and TAP_EVENT_DISABLE implement TAP activation and
+ * deactivation outside the core using scripted code that understands
+ * the specific JTAG router type. They might be triggered indirectly
+ * from EVENT_SETUP operations.
*/
enum jtag_event {
JTAG_TRST_ASSERTED,
+ JTAG_TAP_EVENT_SETUP,
JTAG_TAP_EVENT_ENABLE,
JTAG_TAP_EVENT_DISABLE,
- JTAG_TAP_EVENT_POST_RESET,
};
struct jtag_tap_event_action_s
@@ -643,8 +652,8 @@ extern void jtag_execute_queue_noclear(void);
/// @returns the number of times the scan queue has been flushed
int jtag_get_flush_queue_count(void);
-/// Notify all TAP's about a TLR reset
-void jtag_notify_reset(void);
+/// Report Tcl event to all TAPs
+void jtag_notify_event(enum jtag_event);
/* can be implemented by hw + sw */
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 53c19e1a..212be355 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -41,7 +41,8 @@
#endif
static const Jim_Nvp nvp_jtag_tap_event[] = {
- { .value = JTAG_TAP_EVENT_POST_RESET, .name = "post-reset" },
+ { .value = JTAG_TRST_ASSERTED, .name = "post-reset" },
+ { .value = JTAG_TAP_EVENT_SETUP, .name = "setup" },
{ .value = JTAG_TAP_EVENT_ENABLE, .name = "tap-enable" },
{ .value = JTAG_TAP_EVENT_DISABLE, .name = "tap-disable" },
@@ -373,7 +374,7 @@ static void jtag_tap_handle_event(jtag_tap_t *tap, enum jtag_event e)
for (jteap = tap->event_action; jteap != NULL; jteap = jteap->next) {
if (jteap->event == e) {
- LOG_DEBUG("JTAG tap: %s event: %d (%s) action: %s\n",
+ LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s",
tap->dotted_name,
e,
Jim_Nvp_value2name_simple(nvp_jtag_tap_event, e)->name,
@@ -384,10 +385,12 @@ static void jtag_tap_handle_event(jtag_tap_t *tap, enum jtag_event e)
case JTAG_TAP_EVENT_ENABLE:
case JTAG_TAP_EVENT_DISABLE:
/* NOTE: we currently assume the handlers
- * can't fail. That presumes later code
- * will be verifying the scan chains ...
+ * can't fail. Right here is where we should
+ * really be verifying the scan chains ...
*/
tap->enabled = (e == JTAG_TAP_EVENT_ENABLE);
+ LOG_INFO("JTAG tap: %s %s", tap->dotted_name,
+ tap->enabled ? "enabled" : "disabled");
break;
default:
break;
@@ -586,13 +589,12 @@ static int jim_jtag_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
}
-void jtag_notify_reset(void)
+void jtag_notify_event(enum jtag_event event)
{
jtag_tap_t *tap;
+
for (tap = jtag_all_taps(); tap; tap = tap->next_tap)
- {
- jtag_tap_handle_event(tap, JTAG_TAP_EVENT_POST_RESET);
- }
+ jtag_tap_handle_event(tap, event);
}
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 8cb5dbe0..3c808021 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -277,7 +277,7 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t
return ERROR_OK;
}
-int arm926ejs_examine_debug_reason(target_t *target)
+static int arm926ejs_examine_debug_reason(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -294,7 +294,11 @@ int arm926ejs_examine_debug_reason(target_t *target)
switch (debug_reason)
{
- /* case 0: no debug entry */
+ case 0:
+ LOG_DEBUG("no *NEW* debug entry (?missed one?)");
+ /* ... since last restart or debug reset ... */
+ target->debug_reason = DBG_REASON_DBGRQ;
+ break;
case 1:
LOG_DEBUG("breakpoint from EICE unit 0");
target->debug_reason = DBG_REASON_BREAKPOINT;
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index f6f13cfc..846d90c3 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -67,6 +67,8 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
uint32_t *value, int regnum);
int cortex_a8_dap_write_coreregister_u32(target_t *target,
uint32_t value, int regnum);
+int cortex_a8_assert_reset(target_t *target);
+int cortex_a8_deassert_reset(target_t *target);
target_type_t cortexa8_target =
{
@@ -81,8 +83,8 @@ target_type_t cortexa8_target =
.resume = cortex_a8_resume,
.step = cortex_a8_step,
- .assert_reset = NULL,
- .deassert_reset = NULL,
+ .assert_reset = cortex_a8_assert_reset,
+ .deassert_reset = cortex_a8_deassert_reset,
.soft_reset_halt = NULL,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
@@ -138,8 +140,13 @@ int cortex_a8_init_debug_access(target_t *target)
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
- /* Enabling of instruction execution in debug mode is done in debug_entry code */
-
+ /* Enabling of instruction execution in debug mode is done in debug_entry code */
+
+ /* Resync breakpoint registers */
+
+ /* Since this is likley called from init or reset, update targtet state information*/
+ cortex_a8_poll(target);
+
return retval;
}
@@ -158,8 +165,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
+ {
+ LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
return retval;
}
+ }
while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
@@ -169,8 +179,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
+ {
+ LOG_ERROR("Could not read DSCR register");
return retval;
}
+ }
while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
return retval;
@@ -223,11 +236,25 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
{
int retval;
+ uint32_t dscr;
+
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
+
+ /* Check that DCCRX is not full */
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (dscr & (1 << DSCR_DTR_RX_FULL))
+ {
+ LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+ /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+ }
+
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
/* Move DTRRX to r0 */
@@ -298,12 +325,25 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
+ uint32_t dscr;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+ LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
+ /* Check that DCCRX is not full */
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (dscr & (1 << DSCR_DTR_RX_FULL))
+ {
+ LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+ /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+ }
+
if (Rd > 16)
return retval;
@@ -1188,6 +1228,33 @@ int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
* Cortex-A8 Reset fuctions
*/
+int cortex_a8_assert_reset(target_t *target)
+{
+
+ LOG_DEBUG(" ");
+
+ /* registers are now invalid */
+ armv4_5_invalidate_core_regs(target);
+
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
+}
+
+int cortex_a8_deassert_reset(target_t *target)
+{
+
+ LOG_DEBUG(" ");
+
+ if (target->reset_halt)
+ {
+ int retval;
+ if ((retval = target_halt(target)) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
/*
* Cortex-A8 Memory access
@@ -1265,22 +1332,25 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
exit(-1);
}
- /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
- /* invalidate I-Cache */
- if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+ if (target->state == TARGET_HALTED)
{
- /* Invalidate ICache single entry with MVA, repeat this for all cache
- lines in the address range, Cortex-A8 has fixed 64 byte line length */
- /* Invalidate Cache single entry with MVA to PoU */
- for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
- armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
- }
- /* invalidate D-Cache */
- if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
- {
- /* Invalidate Cache single entry with MVA to PoC */
- for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
- armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
+ /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
+ /* invalidate I-Cache */
+ if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+ {
+ /* Invalidate ICache single entry with MVA, repeat this for all cache
+ lines in the address range, Cortex-A8 has fixed 64 byte line length */
+ /* Invalidate Cache single entry with MVA to PoU */
+ for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+ armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
+ }
+ /* invalidate D-Cache */
+ if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+ {
+ /* Invalidate Cache single entry with MVA to PoC */
+ for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+ armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
+ }
}
return retval;
@@ -1374,7 +1444,7 @@ int cortex_a8_examine(struct target_s *target)
uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("TODO");
-
+
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
@@ -1451,7 +1521,7 @@ int cortex_a8_examine(struct target_s *target)
/* Configure core debug access */
cortex_a8_init_debug_access(target);
-
+
target->type->examined = 1;
return retval;
diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg
index 01557491..866b4a34 100644
--- a/tcl/target/omap2420.cfg
+++ b/tcl/target/omap2420.cfg
@@ -6,11 +6,6 @@ if { [info exists CHIPNAME] } {
} else {
set _CHIPNAME omap2420
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
@@ -46,7 +41,7 @@ jtag newtap $_CHIPNAME jrc -irlen 2 -ircapture 0x1 -irmask 0x3 -expected-id $_JR
# GDB target: the ARM.
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
# scratch: framebuffer, may be initially unavailable in some chips
$_TARGETNAME configure -work-area-phys 0x40210000
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 27e5b007..84460705 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -42,15 +42,20 @@ target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
# FIXME much of this should be in reset event handlers
proc omap3_dbginit { } {
poll off
- reset
sleep 100
jtag tapenable omap3530.dap
targets
# General Cortex A8 debug initialisation
cortex_a8 dbginit
- # Enable DBGU singal for OMAP353x
+ # Enable DBGU signal for OMAP353x
omap3.cpu mww 0x5401d030 0x00002000
poll on
}
+set PRM_RSTCTRL 0x48307250
+
+omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
+omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
+
+
diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg
index fa0fc9e0..30650cfb 100644
--- a/tcl/target/omap5912.cfg
+++ b/tcl/target/omap5912.cfg
@@ -7,13 +7,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME omap5912
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -30,7 +23,7 @@ jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME unknown -irlen 8
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
proc omap5912_reset {} {
#
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 67b3f7a4..2551c3ed 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -6,19 +6,14 @@ if { [info exists CHIPNAME] } {
} else {
set _CHIPNAME dm355
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
# after JTAG reset until ICEpick is used to route them in.
-#set EMU01 "-disable"
+set EMU01 "-disable"
# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
# needing any ICEpick interaction.
-set EMU01 "-enable"
+#set EMU01 "-enable"
source [find target/icepick.cfg]
@@ -33,8 +28,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -44,8 +38,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x07926001
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -55,7 +48,10 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b73b02f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+ "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
@@ -89,7 +85,7 @@ source [find target/davinci.cfg]
# and the ETB memory (4K) are other options, while trace is unused.
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
# and that the work area is used only with a kernel mmu context ...
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 06a52d28..e2d29bd5 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -7,16 +7,15 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME dm365
}
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-#
-# Also note: when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
source [find target/icepick.cfg]
-set EMU01 "-enable"
-#set EMU01 "-disable"
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID ] } {
@@ -24,8 +23,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -35,8 +33,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x0792602f
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -46,8 +43,10 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b83e02f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+ "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index cc23ad44..4dac3d5f 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -7,20 +7,18 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME dm6446
}
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-# Override by setting EMU01 to "-disable".
-#
-# Also note: when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
source [find target/icepick.cfg]
-set EMU01 "-enable"
-#set EMU01 "-disable"
# Subsidiary TAP: unknown ... must enable via ICEpick
-jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable
+jtag newtap $_CHIPNAME unknown -irlen 8 -disable
jtag configure $_CHIPNAME.unknown -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
@@ -35,8 +33,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -46,8 +43,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x07926001
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -57,9 +53,12 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b70002f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+ "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused.
# Little-endian; use the OpenOCD default.
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-19 21:26:50 +0000