diff options
| -rw-r--r-- | src/target/armv7a.c | 24 | ||||
| -rw-r--r-- | src/target/armv7a.h | 5 |
2 files changed, 16 insertions, 13 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 437a2f26..97ce473e 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -307,23 +307,21 @@ static int armv7a_read_mpidr(struct target *target) if (retval != ERROR_OK) goto done; - /* ARMv7R uses a different format for MPIDR. - * When configured uniprocessor (most R cores) it reads as 0. - * This will need to be implemented for multiprocessor ARMv7R cores. */ - if (armv7a->is_armv7r) { - if (mpidr) - LOG_ERROR("MPIDR nonzero in ARMv7-R target"); - goto done; - } - - if (mpidr & 1<<31) { + /* Is register in Multiprocessing Extensions register format? */ + if (mpidr & MPIDR_MP_EXT) { + LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr); armv7a->multi_processor_system = (mpidr >> 30) & 1; + armv7a->multi_threading_processor = (mpidr >> 24) & 1; + armv7a->level2_id = (mpidr >> 16) & 0xf; armv7a->cluster_id = (mpidr >> 8) & 0xf; - armv7a->cpu_id = mpidr & 0x3; - LOG_INFO("%s cluster %x core %x %s", target_name(target), + armv7a->cpu_id = mpidr & 0xf; + LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s", + target_name(target), + armv7a->level2_id, armv7a->cluster_id, armv7a->cpu_id, - armv7a->multi_processor_system == 0 ? "multi core" : "mono core"); + armv7a->multi_processor_system == 0 ? "multi core" : "mono core", + armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT"); } else LOG_ERROR("MPIDR not in multiprocessor format"); diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 1e88c98c..9b1436c7 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -108,6 +108,8 @@ struct armv7a_common { struct adiv5_ap *debug_ap; /* mdir */ uint8_t multi_processor_system; + uint8_t multi_threading_processor; + uint8_t level2_id; uint8_t cluster_id; uint8_t cpu_id; bool is_armv7r; @@ -183,6 +185,9 @@ static inline bool is_armv7a(struct armv7a_common *armv7a) #define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3)) #define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2)) +/* Masks for Multiprocessor Affinity Register */ +#define MPIDR_MP_EXT (1UL << 31) + int armv7a_arch_state(struct target *target); int armv7a_identify_cache(struct target *target); int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a); |