diff options
| -rw-r--r-- | src/target/armv7a.h | 1 | ||||
| -rw-r--r-- | src/target/cortex_a.c | 12 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 3f2bdd34..8d7bece1 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -172,6 +172,7 @@ target_to_armv7a(struct target *target) /* See ARMv7a arch spec section C10.7 */ #define CPUDBG_DSCCR 0x028 +#define CPUDBG_DSMCR 0x02C /* See ARMv7a arch spec section C10.8 */ #define CPUDBG_AUTHSTATUS 0xFB8 diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 5268cf21..61a5df38 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -243,6 +243,18 @@ static int cortex_a_init_debug_access(struct target *target) if (retval != ERROR_OK) return retval; + /* Disable cacheline fills and force cache write-through in debug state */ + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, + armv7a->debug_base + CPUDBG_DSCCR, 0); + if (retval != ERROR_OK) + return retval; + + /* Disable TLB lookup and refill/eviction in debug state */ + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, + armv7a->debug_base + CPUDBG_DSMCR, 0); + if (retval != ERROR_OK) + return retval; + /* Enabling of instruction execution in debug mode is done in debug_entry code */ /* Resync breakpoint registers */ |