- added sam7s256 test example, and test result

git-svn-id: svn://svn.berlios.de/openocd/trunk@415 b42882b7-edfa-0310-969c-e2dbd0fdcd60

11 files changed, 928 insertions, 15 deletions

diff --git a/testing/examples/SAM7S256Test/inc/typedefs.h b/testing/examples/SAM7S256Test/inc/typedefs.h
new file mode 100644
index 00000000..b60ee94b
--- /dev/null
+++ b/testing/examples/SAM7S256Test/inc/typedefs.h
@@ -0,0 +1,50 @@
+/****************************************************************************
+*  Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*  
+*  1. Redistributions of source code must retain the above copyright 
+*     notice, this list of conditions and the following disclaimer.
+*  2. Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in the 
+*     documentation and/or other materials provided with the distribution.
+*  3. Neither the name of the author nor the names of its contributors may 
+*     be used to endorse or promote products derived from this software 
+*     without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 
+*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 
+*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 
+*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
+*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+*  SUCH DAMAGE.
+*
+****************************************************************************
+*  History:
+*
+*  30.03.06  mifi   First Version for Insight tutorial
+****************************************************************************/
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+/*
+ * Some types to use Windows like source
+ */
+typedef char            CHAR;    /* 8-bit signed data    */
+typedef unsigned char   BYTE;    /* 8-bit unsigned data  */
+typedef unsigned short  WORD;    /* 16-bit unsigned data */
+typedef long            LONG;    /* 32-bit signed data   */
+typedef unsigned long   ULONG;   /* 32-bit unsigned data */
+typedef unsigned long   DWORD;   /* 32-bit unsigned data */
+
+
+#endif /* !__TYPEDEFS_H_ */
+/*** EOF ***/
diff --git a/testing/examples/SAM7S256Test/makefile b/testing/examples/SAM7S256Test/makefile
new file mode 100644
index 00000000..9e1e83f8
--- /dev/null
+++ b/testing/examples/SAM7S256Test/makefile
@@ -0,0 +1,146 @@
+#
+#       !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!!    
+#
+##############################################################################################
+# 
+# On command line:
+#
+# make all = Create project
+#
+# make clean = Clean project files.
+#
+# To rebuild project do "make clean" and "make all".
+#
+
+##############################################################################################
+# Start of default section
+#
+
+TRGT = arm-elf-
+CC   = $(TRGT)gcc
+CP   = $(TRGT)objcopy
+AS   = $(TRGT)gcc -x assembler-with-cpp
+BIN  = $(CP) -O ihex 
+
+MCU  = arm7tdmi
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS = 
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS = 
+
+# List all default directories to look for include files here
+DINCDIR = 
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS = 
+
+#
+# End of default section
+##############################################################################################
+
+##############################################################################################
+# Start of user section
+#
+
+# Define project name here
+PROJECT = test
+
+# Define linker script file here
+LDSCRIPT_RAM = ./prj/sam7s256_ram.ld
+LDSCRIPT_ROM = ./prj/sam7s256_rom.ld
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS = 
+
+# Define ASM defines here
+UADEFS = 
+
+# List C source files here
+SRC  = ./src/main.c
+
+# List ASM source files here
+ASRC = ./src/crt.s
+
+# List all user directories here
+UINCDIR = ./inc
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS = 
+
+# Define optimisation level here
+OPT = -O0
+
+#
+# End of user defines
+##############################################################################################
+
+
+INCDIR  = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
+LIBDIR  = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+DEFS    = $(DDEFS) $(UDEFS)
+ADEFS   = $(DADEFS) $(UADEFS)
+OBJS    = $(ASRC:.s=.o) $(SRC:.c=.o)
+LIBS    = $(DLIBS) $(ULIBS)
+MCFLAGS = -mcpu=$(MCU)
+
+ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
+CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS)
+LDFLAGS_RAM = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT_RAM) -Wl,-Map=$(PROJECT)_ram.map,--cref,--no-warn-mismatch $(LIBDIR)
+LDFLAGS_ROM = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT_ROM) -Wl,-Map=$(PROJECT)_rom.map,--cref,--no-warn-mismatch $(LIBDIR)
+
+# Generate dependency information
+CPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+#
+# makefile rules
+#
+
+all: RAM ROM
+
+RAM: $(OBJS) $(PROJECT)_ram.elf $(PROJECT)_ram.hex
+
+ROM: $(OBJS) $(PROJECT)_rom.elf $(PROJECT)_rom.hex
+
+%o : %c
+	$(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@
+
+%o : %s
+	$(AS) -c $(ASFLAGS) $< -o $@
+
+%ram.elf: $(OBJS)
+	$(CC) $(OBJS) $(LDFLAGS_RAM) $(LIBS) -o $@
+
+%rom.elf: $(OBJS)
+	$(CC) $(OBJS) $(LDFLAGS_ROM) $(LIBS) -o $@
+
+%hex: %elf
+	$(BIN) $< $@
+
+clean:
+	-rm -f $(OBJS)
+	-rm -f $(PROJECT)_ram.elf
+	-rm -f $(PROJECT)_ram.map
+	-rm -f $(PROJECT)_ram.hex
+	-rm -f $(PROJECT)_rom.elf
+	-rm -f $(PROJECT)_rom.map
+	-rm -f $(PROJECT)_rom.hex
+	-rm -f $(SRC:.c=.c.bak)
+	-rm -f $(SRC:.c=.lst)
+	-rm -f $(ASRC:.s=.s.bak)
+	-rm -f $(ASRC:.s=.lst)
+	-rm -fR .dep
+
+# 
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
\ No newline at end of file
diff --git a/testing/examples/SAM7S256Test/prj/eclipse_ram.gdb b/testing/examples/SAM7S256Test/prj/eclipse_ram.gdb
new file mode 100644
index 00000000..523cb208
--- /dev/null
+++ b/testing/examples/SAM7S256Test/prj/eclipse_ram.gdb
@@ -0,0 +1,32 @@
+target remote localhost:3333

+monitor reset

+monitor sleep 500

+monitor poll

+monitor soft_reset_halt

+monitor arm7_9 sw_bkpts enable

+

+# WDT_MR, disable watchdog 

+monitor mww 0xFFFFFD44 0x00008000

+

+# RSTC_MR, enable user reset

+monitor mww 0xfffffd08 0xa5000001

+

+# CKGR_MOR

+monitor mww 0xFFFFFC20 0x00000601

+monitor sleep 10

+

+# CKGR_PLLR

+monitor mww 0xFFFFFC2C 0x00481c0e

+monitor sleep 10

+

+# PMC_MCKR

+monitor mww 0xFFFFFC30 0x00000007

+monitor sleep 10

+

+# PMC_IER

+monitor mww 0xFFFFFF60 0x00480100

+monitor sleep 100

+

+load

+break main

+continue

diff --git a/testing/examples/SAM7S256Test/prj/eclipse_rom.gdb b/testing/examples/SAM7S256Test/prj/eclipse_rom.gdb
new file mode 100644
index 00000000..3aabf849
--- /dev/null
+++ b/testing/examples/SAM7S256Test/prj/eclipse_rom.gdb
@@ -0,0 +1,32 @@
+target remote localhost:3333

+monitor reset

+monitor sleep 500

+monitor poll

+monitor soft_reset_halt

+monitor arm7_9 force_hw_bkpts enable

+

+# WDT_MR, disable watchdog 

+monitor mww 0xFFFFFD44 0x00008000

+

+# RSTC_MR, enable user reset

+monitor mww 0xfffffd08 0xa5000001

+

+# CKGR_MOR

+monitor mww 0xFFFFFC20 0x00000601

+monitor sleep 10

+

+# CKGR_PLLR

+monitor mww 0xFFFFFC2C 0x00481c0e

+monitor sleep 10

+

+# PMC_MCKR

+monitor mww 0xFFFFFC30 0x00000007

+monitor sleep 10

+

+# PMC_IER

+monitor mww 0xFFFFFF60 0x00480100

+monitor sleep 100

+

+load

+break main

+continue

diff --git a/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg b/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg
new file mode 100644
index 00000000..e802499c
--- /dev/null
+++ b/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg
@@ -0,0 +1,43 @@
+#daemon configuration

+telnet_port 4444

+gdb_port 3333

+

+# tell gdb our flash memory map

+# and enable flash programming

+gdb_memory_map enable

+gdb_flash_program enable

+

+#interface

+interface ft2232

+ft2232_device_desc "Amontec JTAGkey A"

+ft2232_layout jtagkey

+ft2232_vid_pid 0x0403 0xcff8

+jtag_speed 0

+jtag_nsrst_delay 200

+jtag_ntrst_delay 200

+

+

+#use combined on interfaces or targets that can't set TRST/SRST separately

+reset_config srst_only srst_pulls_trst

+

+#jtag scan chain

+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)

+jtag_device 4 0x1 0xf 0xe

+

+#target configuration

+daemon_startup reset

+

+#target <type> <startup mode>

+#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>

+target arm7tdmi little run_and_init 0 arm7tdmi

+run_and_halt_time 0 30

+

+target_script 0 reset .\prj\sam7s256_reset.script

+

+working_area 0 0x00200000 0x4000 nobackup

+

+#flash bank <driver> <base> <size> <chip_width> <bus_width>

+flash bank at91sam7 0 0 0 0 0

+

+# For more information about the configuration files, take a look at:

+# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger

diff --git a/testing/examples/SAM7S256Test/prj/sam7s256_ram.ld b/testing/examples/SAM7S256Test/prj/sam7s256_ram.ld
new file mode 100644
index 00000000..9fc35c86
--- /dev/null
+++ b/testing/examples/SAM7S256Test/prj/sam7s256_ram.ld
@@ -0,0 +1,132 @@
+/****************************************************************************

+*  Copyright (c) 2006 by Michael Fischer. All rights reserved.

+*

+*  Redistribution and use in source and binary forms, with or without 

+*  modification, are permitted provided that the following conditions 

+*  are met:

+*  

+*  1. Redistributions of source code must retain the above copyright 

+*     notice, this list of conditions and the following disclaimer.

+*  2. Redistributions in binary form must reproduce the above copyright

+*     notice, this list of conditions and the following disclaimer in the 

+*     documentation and/or other materials provided with the distribution.

+*  3. Neither the name of the author nor the names of its contributors may 

+*     be used to endorse or promote products derived from this software 

+*     without specific prior written permission.

+*

+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 

+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 

+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 

+*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 

+*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 

+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 

+*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 

+*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 

+*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 

+*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 

+*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 

+*  SUCH DAMAGE.

+*

+****************************************************************************

+*

+*  History:

+*

+*  30.03.06  mifi   First Version

+****************************************************************************/

+

+

+ENTRY(ResetHandler)

+SEARCH_DIR(.)

+

+/*

+ * Define stack size here

+ */

+FIQ_STACK_SIZE = 0x0100;

+IRQ_STACK_SIZE = 0x0100;

+ABT_STACK_SIZE = 0x0100;

+UND_STACK_SIZE = 0x0100;

+SVC_STACK_SIZE = 0x0400;

+

+

+MEMORY

+{

+  ram : org = 0x00200000, len = 64k

+}

+

+/*

+ * Do not change the next code

+ */

+SECTIONS

+{

+  .text :

+  {

+    *(.vectors);

+    . = ALIGN(4);

+    *(.init);

+    . = ALIGN(4);

+    *(.text);

+    . = ALIGN(4);

+    *(.rodata);

+    . = ALIGN(4);

+    *(.rodata*);

+    . = ALIGN(4);

+    *(.glue_7t);

+    . = ALIGN(4);

+    *(.glue_7);

+    . = ALIGN(4);

+    etext = .;

+  } > ram

+

+  .data :

+  {

+    PROVIDE (__data_start = .);

+    *(.data)

+    . = ALIGN(4);

+    edata = .;

+    _edata = .;

+    PROVIDE (__data_end = .);

+  } > ram

+

+  .bss :

+  {

+    PROVIDE (__bss_start = .);

+    *(.bss)

+    *(COMMON)

+    . = ALIGN(4);

+    PROVIDE (__bss_end = .);

+    

+    . = ALIGN(256);

+    

+    PROVIDE (__stack_start = .);

+    

+    PROVIDE (__stack_fiq_start = .);

+    . += FIQ_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_fiq_end = .);

+

+    PROVIDE (__stack_irq_start = .);

+    . += IRQ_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_irq_end = .);

+

+    PROVIDE (__stack_abt_start = .);

+    . += ABT_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_abt_end = .);

+

+    PROVIDE (__stack_und_start = .);

+    . += UND_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_und_end = .);

+

+    PROVIDE (__stack_svc_start = .);

+    . += SVC_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_svc_end = .);

+    PROVIDE (__stack_end = .);

+    PROVIDE (__heap_start = .);   

+  } > ram

+    

+}

+/*** EOF ***/

+

diff --git a/testing/examples/SAM7S256Test/prj/sam7s256_reset.script b/testing/examples/SAM7S256Test/prj/sam7s256_reset.script
new file mode 100644
index 00000000..ff609b01
--- /dev/null
+++ b/testing/examples/SAM7S256Test/prj/sam7s256_reset.script
@@ -0,0 +1,17 @@
+#

+# Init - taken form the script openocd_at91sam7_ecr.script 

+#

+# I take this script from the following page:

+#

+# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html

+#

+mww 0xfffffd44 0x00008000	# disable watchdog

+mww 0xfffffd08 0xa5000001	# enable user reset

+mww 0xfffffc20 0x00000601	# CKGR_MOR : enable the main oscillator

+sleep 10

+mww 0xfffffc2c 0x00481c0e 	# CKGR_PLLR: 96.1097 MHz

+sleep 10

+mww 0xfffffc30 0x00000007	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz

+sleep 10

+mww 0xffffff60 0x003c0100	# MC_FMR: flash mode (FWS=1,FMCN=60)

+sleep 100

diff --git a/testing/examples/SAM7S256Test/prj/sam7s256_rom.ld b/testing/examples/SAM7S256Test/prj/sam7s256_rom.ld
new file mode 100644
index 00000000..e38746c2
--- /dev/null
+++ b/testing/examples/SAM7S256Test/prj/sam7s256_rom.ld
@@ -0,0 +1,133 @@
+/****************************************************************************

+*  Copyright (c) 2006 by Michael Fischer. All rights reserved.

+*

+*  Redistribution and use in source and binary forms, with or without 

+*  modification, are permitted provided that the following conditions 

+*  are met:

+*  

+*  1. Redistributions of source code must retain the above copyright 

+*     notice, this list of conditions and the following disclaimer.

+*  2. Redistributions in binary form must reproduce the above copyright

+*     notice, this list of conditions and the following disclaimer in the 

+*     documentation and/or other materials provided with the distribution.

+*  3. Neither the name of the author nor the names of its contributors may 

+*     be used to endorse or promote products derived from this software 

+*     without specific prior written permission.

+*

+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 

+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 

+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 

+*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 

+*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 

+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 

+*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 

+*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 

+*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 

+*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 

+*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 

+*  SUCH DAMAGE.

+*

+****************************************************************************

+*

+*  History:

+*

+*  26.01.08  mifi   First Version

+****************************************************************************/

+

+

+ENTRY(ResetHandler)

+SEARCH_DIR(.)

+

+/*

+ * Define stack size here

+ */

+FIQ_STACK_SIZE = 0x0100;

+IRQ_STACK_SIZE = 0x0100;

+ABT_STACK_SIZE = 0x0100;

+UND_STACK_SIZE = 0x0100;

+SVC_STACK_SIZE = 0x0400;

+

+

+MEMORY

+{

+  rom : org = 0x00100000, len = 256k

+  ram : org = 0x00200000, len = 64k

+}

+

+/*

+ * Do not change the next code

+ */

+SECTIONS

+{

+  .text :

+  {

+    *(.vectors);

+    . = ALIGN(4);

+    *(.init);

+    . = ALIGN(4);

+    *(.text);

+    . = ALIGN(4);

+    *(.rodata);

+    . = ALIGN(4);

+    *(.rodata*);

+    . = ALIGN(4);

+    *(.glue_7t);

+    . = ALIGN(4);

+    *(.glue_7);

+    . = ALIGN(4);

+    etext = .;

+  } > rom

+

+  .data :

+  {

+    PROVIDE (__data_start = .);

+    *(.data)

+    . = ALIGN(4);

+    edata = .;

+    _edata = .;

+    PROVIDE (__data_end = .);

+  } > ram

+

+  .bss :

+  {

+    PROVIDE (__bss_start = .);

+    *(.bss)

+    *(COMMON)

+    . = ALIGN(4);

+    PROVIDE (__bss_end = .);

+    

+    . = ALIGN(256);

+    

+    PROVIDE (__stack_start = .);

+    

+    PROVIDE (__stack_fiq_start = .);

+    . += FIQ_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_fiq_end = .);

+

+    PROVIDE (__stack_irq_start = .);

+    . += IRQ_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_irq_end = .);

+

+    PROVIDE (__stack_abt_start = .);

+    . += ABT_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_abt_end = .);

+

+    PROVIDE (__stack_und_start = .);

+    . += UND_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_und_end = .);

+

+    PROVIDE (__stack_svc_start = .);

+    . += SVC_STACK_SIZE;

+    . = ALIGN(4);

+    PROVIDE (__stack_svc_end = .);

+    PROVIDE (__stack_end = .);

+    PROVIDE (__heap_start = .);   

+  } > ram

+    

+}

+/*** EOF ***/

+

diff --git a/testing/examples/SAM7S256Test/src/crt.s b/testing/examples/SAM7S256Test/src/crt.s
new file mode 100644
index 00000000..16e5865e
--- /dev/null
+++ b/testing/examples/SAM7S256Test/src/crt.s
@@ -0,0 +1,225 @@
+/****************************************************************************
+*  Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*  
+*  1. Redistributions of source code must retain the above copyright 
+*     notice, this list of conditions and the following disclaimer.
+*  2. Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in the 
+*     documentation and/or other materials provided with the distribution.
+*  3. Neither the name of the author nor the names of its contributors may 
+*     be used to endorse or promote products derived from this software 
+*     without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 
+*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 
+*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 
+*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
+*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+*  SUCH DAMAGE.
+*
+****************************************************************************
+*
+*  History:
+*
+*  18.12.06  mifi   First Version
+*                   The hardware initialization is based on the startup file
+*                   crtat91sam7x256_rom.S from NutOS 4.2.1. 
+*                   Therefore partial copyright by egnite Software GmbH.
+****************************************************************************/
+
+/*
+ * Some defines for the program status registers
+ */
+   ARM_MODE_USER  = 0x10      /* Normal User Mode                             */ 
+   ARM_MODE_FIQ   = 0x11      /* FIQ Fast Interrupts Mode                     */
+   ARM_MODE_IRQ   = 0x12      /* IRQ Standard Interrupts Mode                 */
+   ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                   */
+   ARM_MODE_ABORT = 0x17      /* Abort Processing memory Faults Mode          */
+   ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                  */
+   ARM_MODE_SYS   = 0x1F      /* System Running in Priviledged Operating Mode */
+   ARM_MODE_MASK  = 0x1F
+   
+   I_BIT          = 0x80      /* disable IRQ when I bit is set */
+   F_BIT          = 0x40      /* disable IRQ when I bit is set */
+   
+/*
+ * Register Base Address
+ */
+   AIC_BASE         = 0xFFFFF000
+   AIC_EOICR_OFF    = 0x130
+   AIC_IDCR_OFF     = 0x124
+
+   RSTC_MR          = 0xFFFFFD08
+   RSTC_KEY         = 0xA5000000
+   RSTC_URSTEN      = 0x00000001
+
+   WDT_BASE         = 0xFFFFFD40
+   WDT_MR_OFF       = 0x00000004
+   WDT_WDDIS        = 0x00008000
+
+   MC_BASE          = 0xFFFFFF00
+   MC_FMR_OFF       = 0x00000060
+   MC_FWS_1FWS      = 0x00480100
+      
+   .section .vectors,"ax"
+   .code 32
+        
+/****************************************************************************/
+/*               Vector table and reset entry                               */
+/****************************************************************************/
+_vectors:
+   ldr pc, ResetAddr    /* Reset                 */
+   ldr pc, UndefAddr    /* Undefined instruction */
+   ldr pc, SWIAddr      /* Software interrupt    */
+   ldr pc, PAbortAddr   /* Prefetch abort        */
+   ldr pc, DAbortAddr   /* Data abort            */
+   ldr pc, ReservedAddr /* Reserved              */
+   ldr pc, IRQAddr      /* IRQ interrupt         */
+   ldr pc, FIQAddr      /* FIQ interrupt         */
+
+
+ResetAddr:     .word ResetHandler
+UndefAddr:     .word UndefHandler
+SWIAddr:       .word SWIHandler
+PAbortAddr:    .word PAbortHandler
+DAbortAddr:    .word DAbortHandler
+ReservedAddr:  .word 0
+IRQAddr:       .word IRQHandler
+FIQAddr:       .word FIQHandler
+
+   .ltorg
+
+   .section .init, "ax"
+   .code 32
+   
+   .global ResetHandler
+   .global ExitFunction
+   .extern main
+/****************************************************************************/
+/*                           Reset handler                                  */
+/****************************************************************************/
+ResetHandler:
+   /*
+    * The watchdog is enabled after processor reset. Disable it.
+    */
+   ldr   r1, =WDT_BASE
+   ldr   r0, =WDT_WDDIS
+   str   r0, [r1, #WDT_MR_OFF]
+
+   
+   /*
+    * Enable user reset: assertion length programmed to 1ms
+    */
+   ldr   r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
+   ldr   r1, =RSTC_MR
+   str   r0, [r1, #0]
+
+   
+   /*
+    * Use 2 cycles for flash access.
+    */
+   ldr   r1, =MC_BASE
+   ldr   r0, =MC_FWS_1FWS
+   str   r0, [r1, #MC_FMR_OFF]
+
+
+   /*
+    * Disable all interrupts. Useful for debugging w/o target reset.
+    */
+   ldr   r1, =AIC_BASE
+   mvn   r0, #0
+   str   r0, [r1, #AIC_EOICR_OFF]
+   str   r0, [r1, #AIC_IDCR_OFF]
+
+    
+   /*
+    * Setup a stack for each mode
+    */    
+   msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */     
+   ldr   sp, =__stack_und_end
+   
+   msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */
+   ldr   sp, =__stack_abt_end
+   
+   msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */   
+   ldr   sp, =__stack_fiq_end
+   
+   msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */   
+   ldr   sp, =__stack_irq_end
+   
+   msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */
+   ldr   sp, =__stack_svc_end
+
+
+   /*
+    * Clear .bss section
+    */
+   ldr   r1, =__bss_start
+   ldr   r2, =__bss_end
+   ldr   r3, =0
+bss_clear_loop:
+   cmp   r1, r2
+   strne r3, [r1], #+4
+   bne   bss_clear_loop
+   
+   
+   /*
+    * Jump to main
+    */
+   mrs   r0, cpsr
+   bic   r0, r0, #I_BIT | F_BIT     /* Enable FIQ and IRQ interrupt */
+   msr   cpsr, r0
+   
+   mov   r0, #0 /* No arguments */
+   mov   r1, #0 /* No arguments */
+   ldr   r2, =main
+   mov   lr, pc
+   bx    r2     /* And jump... */
+                       
+ExitFunction:
+   nop
+   nop
+   nop
+   b ExitFunction   
+   
+
+/****************************************************************************/
+/*                         Default interrupt handler                        */
+/****************************************************************************/
+
+UndefHandler:
+   b UndefHandler
+   
+SWIHandler:
+   b SWIHandler
+
+PAbortHandler:
+   b PAbortHandler
+
+DAbortHandler:
+   b DAbortHandler
+   
+IRQHandler:
+   b IRQHandler
+   
+FIQHandler:
+   b FIQHandler
+   
+   .weak ExitFunction
+   .weak UndefHandler, PAbortHandler, DAbortHandler
+   .weak IRQHandler, FIQHandler
+
+   .ltorg
+/*** EOF ***/   
+  
+
diff --git a/testing/examples/SAM7S256Test/src/main.c b/testing/examples/SAM7S256Test/src/main.c
new file mode 100644
index 00000000..4579f17e
--- /dev/null
+++ b/testing/examples/SAM7S256Test/src/main.c
@@ -0,0 +1,91 @@
+/****************************************************************************
+*  Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*  
+*  1. Redistributions of source code must retain the above copyright 
+*     notice, this list of conditions and the following disclaimer.
+*  2. Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in the 
+*     documentation and/or other materials provided with the distribution.
+*  3. Neither the name of the author nor the names of its contributors may 
+*     be used to endorse or promote products derived from this software 
+*     without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 
+*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 
+*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 
+*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
+*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+*  SUCH DAMAGE.
+*
+****************************************************************************
+*  History:
+*
+*  30.03.06  mifi   First Version for Insight tutorial
+*  26.01.08  mifi   Added variable "d" to test const variable.
+****************************************************************************/
+#define __MAIN_C__
+
+/*
+ * I use the include only, to show
+ * how to setup a include dir in the makefile
+ */
+#include "typedefs.h"
+
+/*=========================================================================*/
+/*  DEFINE: All Structures and Common Constants                            */
+/*=========================================================================*/
+
+/*=========================================================================*/
+/*  DEFINE: Prototypes                                                     */
+/*=========================================================================*/
+
+/*=========================================================================*/
+/*  DEFINE: Definition of all local Data                                   */
+/*=========================================================================*/
+static const DWORD d = 7;
+
+/*=========================================================================*/
+/*  DEFINE: Definition of all local Procedures                             */
+/*=========================================================================*/
+
+/*=========================================================================*/
+/*  DEFINE: All code exported                                              */
+/*=========================================================================*/
+/***************************************************************************/
+/*  main                                                                   */
+/***************************************************************************/
+int main (void)
+{
+  DWORD a = 1;
+  DWORD b = 2;
+  DWORD c = 0;
+  
+  a = a + d;
+    
+  while (1)
+  {
+    a++;
+    b++;
+    c = a + b;
+  }
+  
+  /*
+   * This return here make no sense.
+   * But to prevent the compiler warning:
+   * "return type of 'main' is not 'int'
+   * we use an int as return :-)
+   */ 
+  return(0);
+}
+
+/*** EOF ***/
diff --git a/testing/index.html b/testing/index.html
index 716eb808..6be68893 100644
--- a/testing/index.html
+++ b/testing/index.html
@@ -32,91 +32,103 @@
 		<table border="1">
 			<tr>
 				<th width="65">ID</th>
-				<th width="150">Synopsis</th>
+				<th width="165">Synopsis</th>
 				<th align="center" width="110">Passed version</th>
 				<th align="center" width="110">Broken version</th>
 			</tr>
 			<tr>
 				<td width="65">ocd1</td>
-				<td width="150">Telnet Windows</td>
+				<td width="165">Telnet Windows</td>
 				<td align="center" width="110">291</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65">ocd2</td>
-				<td width="150">Telnet Linux</td>
+				<td width="165">Telnet Linux</td>
 				<td align="center" width="110">291</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65">ocd3</td>
-				<td width="150">Telnet Cygwin</td>
+				<td width="165">Telnet Cygwin</td>
 				<td align="center" width="110">291</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#test_ocd4">ocd4</a></td>
-				<td width="150">ARM7 debugging</td>
+				<td width="165">ARM7 debugging</td>
 				<td align="center" width="110">291</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65">xscale1</td>
-				<td width="150">XScale debugging</td>
+				<td width="165">XScale debugging</td>
 				<td align="center" width="110">291</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65">xscale2</td>
-				<td width="150">XScale MMU</td>
+				<td width="165">XScale MMU</td>
 				<td align="center" width="110">291</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#bdte-ram">bdte-ram</a></td>
-				<td width="150">str710 ram debugging</td>
+				<td width="165">str710 ram debugging</td>
 				<td align="center" width="110">320</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#bdte-rom">bdte-rom</a></td>
-				<td width="150">str710 rom debugging</td>
+				<td width="165">str710 rom debugging</td>
 				<td align="center" width="110">320</td>
 				<td align="center" width="110"><b>406</b></td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#bdte-ram">bdte-ram</a></td>
-				<td width="150">str912 ram debugging</td>
+				<td width="165">str912 ram debugging</td>
 				<td align="center" width="110">320</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#bdte-rom">bdte-rom</a></td>
-				<td width="150">str912 rom debugging</td>
+				<td width="165">str912 rom debugging</td>
 				<td align="center" width="110">320</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#bdte-ram">bdte-ram</a></td>
-				<td width="150">lpc2148 ram debugging</td>
+				<td width="165">lpc2148 ram debugging</td>
 				<td align="center" width="110">320</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#bdte-rom">bdte-rom</a></td>
-				<td width="150">lpc2148 rom debugging</td>
+				<td width="165">lpc2148 rom debugging</td>
 				<td align="center" width="110">320</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#bdte-ram">bdte-ram</a></td>
-				<td width="150">lpc2294 ram debugging</td>
+				<td width="165">lpc2294 ram debugging</td>
 				<td align="center" width="110">320</td>
 				<td align="center" width="110">n/a</td>
 			</tr>
 			<tr>
 				<td width="65"><a href="#bdte-rom">bdte-rom</a></td>
-				<td width="150">lpc2294 rom debugging</td>
+				<td width="165">lpc2294 rom debugging</td>
+				<td align="center" width="110">320</td>
+				<td align="center" width="110">n/a</td>
+			</tr>
+			<tr>
+				<td width="65"><a href="#bdte-ram">bdte-ram</a></td>
+				<td width="165">sam7s256 ram debugging</td>
+				<td align="center" width="110">320</td>
+				<td align="center" width="110">n/a</td>
+			</tr>
+			<tr>
+				<td width="65"><a href="#bdte-rom">bdte-rom</a></td>
+				<td width="165">sam7s256 rom debugging</td>
 				<td align="center" width="110">320</td>
 				<td align="center" width="110">n/a</td>
 			</tr>