Remove annoying end-of-line whitespace from tcl/* files

git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60

85 files changed, 682 insertions, 683 deletions

diff --git a/tcl/bitsbytes.tcl b/tcl/bitsbytes.tcl
index 9129ae0a..3f65c209 100644
--- a/tcl/bitsbytes.tcl
+++ b/tcl/bitsbytes.tcl
@@ -22,7 +22,7 @@ for { set x 1  } { $x < 2048 } { set x [expr $x * 2]} {
 # Create M bytes values
 #    __1M ... to __2048K
 for { set x 1  } { $x < 2048 } { set x [expr $x * 2]} {
-    set vn [format "__%dM" $x] 
+    set vn [format "__%dM" $x]
     global $vn
     set $vn [expr (1024 * 1024 * $x)]
 }
diff --git a/tcl/board/arm_evaluator7t.cfg b/tcl/board/arm_evaluator7t.cfg
index 9cca2391..52de57af 100644
--- a/tcl/board/arm_evaluator7t.cfg
+++ b/tcl/board/arm_evaluator7t.cfg
@@ -2,7 +2,7 @@
 
 source [find target/samsung_s3c4510.cfg]
 
-# 
+#
 # FIXME:
 #  Add (A) sdram configuration
 #  Add (B) flash cfi programing configuration
diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg
index 900ee351..9a6f89e6 100644
--- a/tcl/board/at91rm9200-dk.cfg
+++ b/tcl/board/at91rm9200-dk.cfg
@@ -16,7 +16,7 @@ proc at91rm9200_dk_init { } {
     # Try to run at 1khz... Yea, that slow!
     # Chip is really running @ 32khz
     jtag_khz 8
-    
+
     mww 0xfffffc64 0xffffffff
     ##  disable all clocks but system clock
     mww 0xfffffc04 0xfffffffe
@@ -37,14 +37,14 @@ proc at91rm9200_dk_init { } {
     mww 0xfffffc30 0x202
     ## Sleep some - (go read)
     sleep 100
-    
+
     #========================================
     # CPU now runs at 180mhz
     # SYS runs at 60mhz.
     jtag_khz 40000
     #========================================
-    
-    
+
+
     ##  set memc for all memories
     mww 0xffffff60 0x02
     ##  program smc controller
@@ -55,7 +55,7 @@ proc at91rm9200_dk_init { } {
     mww 0xffffff80 0x02
     ##  touch sdram chip to make it work
     mww 0x20000000 0
-    ##  sdram controller mode register 
+    ##  sdram controller mode register
     mww 0xffffff90 0x04
     mww 0x20000000 0
     mww 0x20000000 0
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index c9deb144..00ab7faf 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -62,7 +62,7 @@ proc read_register {register} {
 }
 
 proc at91sam9g20_init { } {
-	
+
 	# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
 	# a number of steps that must be carefully performed.  The process outline below follows the
 	# recommended procedure outlined in the AT91SAM9G20 technical manual.
@@ -94,7 +94,7 @@ proc at91sam9g20_init { } {
 
 	mww 0xfffffc30 0x00000101
 	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-	
+
 	# Now change PMC_MCKR register to select PLLA.
 	# Wait for MCKRDY signal from PMC_SR to assert.
 
diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg
index 0d9d0026..099d93df 100644
--- a/tcl/board/atmel_at91sam9260-ek.cfg
+++ b/tcl/board/atmel_at91sam9260-ek.cfg
@@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start {
         # RSTC_MR : enable user reset, MMU may be enabled... use physical address
         arm926ejs mww_phys 0xfffffd08 0xa5000501
 }
-	
+
 $_TARGETNAME configure -event reset-init {
         mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
 
@@ -48,7 +48,7 @@ $_TARGETNAME configure -event reset-init {
 
 	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
         mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
-        
+
         mww 0xffffef1c 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
 
 	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
diff --git a/tcl/board/crossbow_tech_imote2.cfg b/tcl/board/crossbow_tech_imote2.cfg
index 7e9d487c..a7d12156 100644
--- a/tcl/board/crossbow_tech_imote2.cfg
+++ b/tcl/board/crossbow_tech_imote2.cfg
@@ -4,7 +4,7 @@ set  CHIPNAME imote2
 source [find target/pxa270.cfg]
 
 # longer-than-normal reset delay
-jtag_nsrst_delay 800 
+jtag_nsrst_delay 800
 
 reset_config trst_and_srst separate
 
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 8bf77cb3..17873230 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -11,7 +11,7 @@ $_TARGETNAME configure -event reset-init { csb732_init }
 
 # Bare-bones initialization of core clocks and SDRAM
 proc csb732_init { } {
-	
+
 	# Disable fast writing only for init
 	memwrite burst disable
 
@@ -29,17 +29,17 @@ proc csb732_init { } {
 
 	# Set ARM clock to 532 MHz, AHB to 133 MHz
 	mww 0x53F80004 0x1000
-	
+
 	# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
 	mww 0x53F8001C 0xB2C01
-	
+
 	set ESDMISC 0xB8001010
 	set ESDCFG0 0xB8001004
 	set ESDCTL0 0xB8001000
 
 	# Enable DDR
 	mww $ESDMISC 0x4
-	
+
 	# Timing
 	mww $ESDCFG0 0x007fff3f
 
@@ -51,7 +51,7 @@ proc csb732_init { } {
 
 	# Enable CS) auto-refresh
 	mww $ESDCTL0 0xA2120080
-	
+
 	# Refresh twice (dummy writes)
 	mww 0x80000000 0
 	mww 0x80000000 0
@@ -59,7 +59,7 @@ proc csb732_init { } {
 	# Enable CS0 load mode register
 	mww $ESDCTL0 0xB2120080
 
-	# Dummy writes	
+	# Dummy writes
 	mwb 0x80000033 0x01
 	mwb 0x81000000 0x01
 
diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg
index f8b89122..58f12a68 100644
--- a/tcl/board/digi_connectcore_wi-9c.cfg
+++ b/tcl/board/digi_connectcore_wi-9c.cfg
@@ -4,15 +4,15 @@
 
 reset_config trst_and_srst
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME ns9360
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
   # This config file was defaulting to big endian..
    set  _ENDIAN big
 }
@@ -46,17 +46,17 @@ $_TARGETNAME configure -event reset-init {
 	mww 0x90600104 0x33313333
 	mww 0xA0700000 0x00000001  # Enable the memory controller.
 	mww 0xA0700024 0x00000006  # Set the refresh counter 6
-	mww 0xA0700028 0x00000001  # 
+	mww 0xA0700028 0x00000001  #
 	mww 0xA0700030 0x00000001  # Set the precharge period
 	mww 0xA0700034 0x00000004  # Active to precharge command period is 16 clock cycles
 	mww 0xA070003C 0x00000001  # tAPR
 	mww 0xA0700040 0x00000005  # tDAL
 	mww 0xA0700044 0x00000001  # tWR
-	mww 0xA0700048 0x00000006  # tRC 32 clock cycles  
+	mww 0xA0700048 0x00000006  # tRC 32 clock cycles
 	mww 0xA070004C 0x00000006  # tRFC 32 clock cycles
 	mww 0xA0700054 0x00000001  # tRRD
 	mww 0xA0700058 0x00000001  # tMRD
-	mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4) 
+	mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4)
 	mww 0xA0700120 0x00004280  # Dynamic Config 1 (cs5)
 	mww 0xA0700140 0x00004280  # Dynamic Config 2 (cs6)
 	mww 0xA0700160 0x00004280  # Dynamic Config 3 (cs7)
@@ -79,11 +79,11 @@ $_TARGETNAME configure -event reset-init {
 	mww 0xA0900000 0x00000002
 	mww 0xA0900000 0x00000002
 	#
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
 	#
 	mww 0xA0700024 0x00000030 # Set the refresh counter to 30
 	mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
diff --git a/tcl/board/eir.cfg b/tcl/board/eir.cfg
index 08765658..3754a422 100644
--- a/tcl/board/eir.cfg
+++ b/tcl/board/eir.cfg
@@ -4,7 +4,7 @@
 source [find target/sam7se512.cfg]
 
 $_TARGETNAME configure -event reset-init {
-	# WDT_MR, disable watchdog 
+	# WDT_MR, disable watchdog
 	mww 0xFFFFFD44 0x00008000
 
 	# RSTC_MR, enable user reset
@@ -51,31 +51,31 @@ $_TARGETNAME configure -event reset-init {
 
 	# Issue 16 bit SDRAM command: NOP
 	mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 
 	# Issue 16 bit SDRAM command: Precharge all
 	mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 
 	# Issue 8 auto-refresh cycles
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 
-	# Issue 16 bit SDRAM command: Set mode register  
+	# Issue 16 bit SDRAM command: Set mode register
 	mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
 	mww 0x20000014 0xcafedede
 
diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg
index de4d56dd..25ff784d 100644
--- a/tcl/board/hitex_str9-comstick.cfg
+++ b/tcl/board/hitex_str9-comstick.cfg
@@ -14,15 +14,15 @@ reset_config trst_and_srst
 #jtag scan chain
 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME str912
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -56,10 +56,10 @@ target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
 	#jtag_rclk 3000
-	
+
 	# -- Enable 96K RAM
 	# PFQBC enabled / DTCM & AHB wait-states disabled
-	mww 0x5C002034 0x0191 
+	mww 0x5C002034 0x0191
 
 	str9x flash_config 0 4 2 0 0x80000
 	flash protect 0 0 7 off
diff --git a/tcl/board/imx27ads.cfg b/tcl/board/imx27ads.cfg
index dc0de4a6..664b4705 100644
--- a/tcl/board/imx27ads.cfg
+++ b/tcl/board/imx27ads.cfg
@@ -24,52 +24,52 @@ proc imx27ads_init { } {
 	# ========================================
 	#  Configure DDR on CSD0 -- initial reset
 	# ========================================
-	mww 0xD8001010 0x00000008 
+	mww 0xD8001010 0x00000008
 
 	# ========================================
-	#  Configure PSRAM on CS5 
+	#  Configure PSRAM on CS5
 	# ========================================
 	mww 0xd8002050 0x0000dcf6
-	mww 0xd8002054 0x444a4541 
-	mww 0xd8002058 0x44443302 
+	mww 0xd8002054 0x444a4541
+	mww 0xd8002058 0x44443302
 
 	#  ========================================
 	#         Configure16 bit NorFlash on CS0
 	#  ========================================
-	mww 0xd8002000 0x0000CC03 
-	mww 0xd8002004 0xa0330D01 
-	mww 0xd8002008 0x00220800 
+	mww 0xd8002000 0x0000CC03
+	mww 0xd8002004 0xa0330D01
+	mww 0xd8002008 0x00220800
 
 	# ========================================
-	#  Configure CPLD on CS4 
+	#  Configure CPLD on CS4
 	# ========================================
-	mww 0xd8002040 0x0000DCF6 
-	mww 0xd8002044 0x444A4541 
-	mww 0xd8002048 0x44443302 
+	mww 0xd8002040 0x0000DCF6
+	mww 0xd8002044 0x444A4541
+	mww 0xd8002048 0x44443302
 
 	# ========================================
-	#  Configure DDR on CSD0 -- wait 5000 cycle 
+	#  Configure DDR on CSD0 -- wait 5000 cycle
 	# ========================================
-	mww 0x10027828 0x55555555 
-	mww 0x10027830 0x55555555 
-	mww 0x10027834 0x55555555 
-	mww 0x10027838 0x00005005 
-	mww 0x1002783C 0x15555555 
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
 
-	mww 0xD8001010 0x00000004 
+	mww 0xD8001010 0x00000004
 
-	mww 0xD8001004 0x00795729 
+	mww 0xD8001004 0x00795729
 
-	mww 0xD8001000 0x92200000 
+	mww 0xD8001000 0x92200000
 	mww 0xA0000F00 0x0
 
-	mww 0xD8001000 0xA2200000 
+	mww 0xD8001000 0xA2200000
 	mww 0xA0000F00 0x0
 	mww 0xA0000F00 0x0
 
-	mww 0xD8001000 0xB2200000 
+	mww 0xD8001000 0xB2200000
 	mwb 0xA0000033 0x