diff options
| author | Paul Fertser <fercerpav@gmail.com> | 2013-11-07 23:26:45 +0400 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-12-19 19:54:55 +0000 |
| commit | da7f048104c49b9a4826b9ee47e6f68b43d1f987 (patch) | |
| tree | 55aa70587d0e8801825d52a5cea4971bf993c8a4 /tcl | |
| parent | 03e9729043cb51c6c384d29b97a039660705e170 (diff) | |
target: add kl25z HLA (stlink) config
Based on Nemuisan Tokusei's. Untested, but original config was reported
to work ok.
Change-Id: Ic991dce55bfca266880081fe2bbd9e6e263b0fc0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1803
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/kl25z_hla.cfg | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/tcl/target/kl25z_hla.cfg b/tcl/target/kl25z_hla.cfg new file mode 100644 index 00000000..218a28d9 --- /dev/null +++ b/tcl/target/kl25z_hla.cfg @@ -0,0 +1,55 @@ +# MKL25Z128VLK4 +# FreeScale Cortex-M0plus with 128kB Flash and 16kB Local On-Chip SRAM + +if { [info exists CHIPNAME] == 0 } { + set _CHIPNAME kl25z +} + +if { [info exists CPUTAPID] == 0 } { + set _CPUTAPID 0x0BC11477 +} + +if { [info exists WORKAREASIZE] == 0 } { + set _WORKAREASIZE 0x3000 +} + +if { [info exists TRANSPORT] == 0 } { + set _TRANSPORT hla_swd +} + +transport select $_TRANSPORT + +hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME hla_target -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank pflash kinetis 0x00000000 0x20000 0 4 $_TARGETNAME + +proc kl25z_enable_pll {} { + echo "KL25Z: Enabling PLL" + # SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */ + mww 0x40048044 0x00020000 + # /* Switch to FEI Mode */ + # MCG->C1 = (uint8_t)0x06U; + mwb 0x40064000 0x06 + # MCG->C2 = (uint8_t)0x00U; + mwb 0x40064001 0x00 + # /* MCG->C4: DMX32=0,DRST_DRS=1 */ + # MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U); + mwb 0x40064003 0x37 + #OSC0->CR = (uint8_t)0x80U; + mwb 0x40065000 0x80 + # MCG->C5 = (uint8_t)0x00U; + mwb 0x40064004 0x00 + # MCG->C6 = (uint8_t)0x00U; + mwb 0x40064005 0x00 + sleep 100 +} + +$_TARGETNAME configure -event reset-init { + kl25z_enable_pll +} + |