diff options
| author | is2t <devel@is2t.com> | 2012-12-07 08:15:03 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-12-11 12:42:32 +0000 |
| commit | 1e07f7bb6a3bb667b5401ffd94ac7985d91fb6cc (patch) | |
| tree | 607a4fa67a53fd875a8770c0cc3555c4d123fde8 /tcl | |
| parent | 71d43007c6a3fe32cfcac0712b294029ced4c61b (diff) | |
LPC1788 target configuration file.
Change-Id: I68bd6b7c19d9d1bee13d0921c32b4490e68ab8f2
Signed-off-by: is2t <devel@is2t.com>
Reviewed-on: http://openocd.zylin.com/1002
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/lpc1788.cfg | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tcl/target/lpc1788.cfg b/tcl/target/lpc1788.cfg new file mode 100644 index 00000000..16b62c8a --- /dev/null +++ b/tcl/target/lpc1788.cfg @@ -0,0 +1,20 @@ +# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM, +set CHIPNAME lpc1788 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x10000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~12MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 12000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; + +# if srst is not fitted, use SYSRESETREQ to perform a soft reset +cortex_m3 reset_config sysresetreq |