diff options
| author | Tomas Vanek <vanekt@fbl.cz> | 2015-03-14 12:03:47 +0100 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-04-14 15:47:43 +0100 |
| commit | f3b1405fddf0b32af27ad3894841f7d1702d8e5a (patch) | |
| tree | fb42b39ef1149ff613bd2b7a94b270be0ea16981 /tcl | |
| parent | bdfd5bbe0473d9db7949dd303bcb28282a17a47d (diff) | |
AT91SAM4L: handle reset run/halt in SMAP
This is a remake of http://openocd.zylin.com/1966
originally written by Angus Gratton <gus@projectgus.com>
ATSAM4L has a "System Manager Access Port" (SMAP) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Without this change any use of sysresetreq or srst locks the chip
in reset state until power is cycled.
A new function smap_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and SMAP reset is released then.
Change-Id: Iad736357b0f551725befa2b9e00f3bc54504f3d8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2604
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/at91sam4lXX.cfg | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg index 93799a23..46c38aef 100644 --- a/tcl/target/at91sam4lXX.cfg +++ b/tcl/target/at91sam4lXX.cfg @@ -5,3 +5,23 @@ source [find target/at91sam4XXX.cfg] set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME + +# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N +# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3). +# +# smap_reset_deassert configures whether we want to run or halt out of reset, +# then instruct the SMAP to let us out of reset. +$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert" + +# SRST (wired to RESET_N) resets debug circuitry +# srst_pulls_trst is not configured here to avoid an error raised in reset halt +reset_config srst_gates_jtag + +# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed. +# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio. +# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2 +# but your mileage may vary. +adapter_khz 50 + +# System RC oscillator RCSYS starts in 3 cycles +adapter_nsrst_delay 0 |