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authorAntonio Borneo <borneo.antonio@gmail.com>2011-11-21 11:46:59 +0800
committerSpencer Oliver <spen@spen-soft.co.uk>2011-11-21 22:07:50 +0000
commit40d9b241954d8b5ac0baa105a76eb2ded175d138 (patch)
tree081cb60310771c658733b2778235e5eeef2078ae /tcl
parent841ee77350a0119f6fdc65dbe72c991bca9e9c4f (diff)
TCL/SPEAr: move DDR activation in common code
DDR controller activation should not be in DDR chip specific code, but in generic DDR controller part. Change-Id: If1b178228352b48b0097d7b9b300005fb5bb4fb6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/228 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl')
-rw-r--r--tcl/chip/st/spear/spear3xx_ddr.tcl5
1 files changed, 3 insertions, 2 deletions
diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl
index 14b5dfe0..9021cf7d 100644
--- a/tcl/chip/st/spear/spear3xx_ddr.tcl
+++ b/tcl/chip/st/spear/spear3xx_ddr.tcl
@@ -18,6 +18,9 @@ proc sp3xx_ddr_init {ddr_type} {
error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
}
+ # MPMC START
+ mww 0xfc60001c 0x01000100
+
# Check for single/double memory chip
# DDR starts at address 0x00000000
mww $ddr_size 0x87654321
@@ -115,6 +118,4 @@ proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {} {
mww 0xfc6001a8 0x00000000 ;# MEMCTL_LWPWR_REG
mww 0xfc6001ac 0x00860000 ;# MEMCTL_GP_15
mww 0xfc6001b0 0x00000002 ;# MEMCTL_TPDEX
- # MPMC START
- mww 0xfc60001c 0x01000100
}