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authorTarek BOCHKATI <tarek.bouchkati@gmail.com>2020-01-06 17:19:31 +0100
committerTomas Vanek <vanekt@fbl.cz>2020-01-16 09:38:52 +0000
commita6a642bf72a12c9a1fc4b92de2dc46d12cb3b58e (patch)
treea98bf06b82916871f50dad7a68c9e9b6a7bccc3c /tcl
parent8536306b6ebcee8249376734d64db40a07916c9d (diff)
flash/nor: add support of STM32WB on top STM32L4 flash driver
Change-Id: I9fb6700085d817d35a691f6484193f67939a4e0f Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4933 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl')
-rw-r--r--tcl/target/stm32wbx.cfg103
1 files changed, 103 insertions, 0 deletions
diff --git a/tcl/target/stm32wbx.cfg b/tcl/target/stm32wbx.cfg
new file mode 100644
index 00000000..138bcf18
--- /dev/null
+++ b/tcl/target/stm32wbx.cfg
@@ -0,0 +1,103 @@
+# script for stm32wbx family
+
+#
+# stm32wb devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32wbx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ if { [using_jtag] } {
+ set _CPUTAPID 0x6ba00477
+ } else {
+ # SWD IDCODE (single drop, arm)
+ set _CPUTAPID 0x6ba02477
+ }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter_khz 500
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+ # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+ # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+ # 2 WS compliant with VOS=Range1 and 24 MHz.
+ mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency)
+ mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+ # Boost JTAG frequency
+ adapter_khz 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+ # Reset clock is MSI (4 MHz)
+ adapter_khz 500
+}
+
+$_TARGETNAME configure -event examine-end {
+ # Enable debug during low power modes (uses more power)
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+ mmw 0xE0042004 0x00000007 0
+
+ # Stop watchdog counters during halt
+ # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+ mmw 0xE004203C 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+ # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+ # change this value accordingly to configure trace pins
+ # assignment
+ mmw 0xE0042004 0x00000020 0
+}