diff options
| author | Pawel Si <stawel+openocd@gmail.com> | 2014-12-06 17:31:18 +0100 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-02-11 15:23:09 +0000 |
| commit | b01952d78cc82b192c66664b7c59df728c4f22fe (patch) | |
| tree | a3ba37d34983b58cd20514a55d4af11ddcd8a613 /tcl/target | |
| parent | 45a86f8e2a58c7c0acb6328a660846946e81ed1c (diff) | |
mini51: support for Nuvoton NuMicro M051 series flash memory
adds flash support for Nuvoton M052, M054, M058, M0516 microcontrollers
into the mini51 driver, patch also adds support for programing LDROM,
flash data and flash config.
I've tested it on a M0516LBN microcontroller using an ST-LINK/V2:
1. removing security lock:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "init ; halt ; mini51 chip_erase; exit"
2. flashing:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "program file.hex"
Change-Id: I918bfbb42461279c216fb9c22272d77501a2f202
Signed-off-by: Pawel Si <stawel+openocd@gmail.com>
Reviewed-on: http://openocd.zylin.com/2426
Tested-by: jenkins
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/m051.cfg | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/tcl/target/m051.cfg b/tcl/target/m051.cfg new file mode 100644 index 00000000..d0655947 --- /dev/null +++ b/tcl/target/m051.cfg @@ -0,0 +1,61 @@ +# script for nuvoton M051 family + +transport select hla_swd + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME m051 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0091 + # Section 29.5.3 + set _CPUTAPID 0x0bb11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash_aprom +flash bank $_FLASHNAME mini51 0x00000000 0x4000 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_data +flash bank $_FLASHNAME mini51 0x0001F000 0x1000 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_ldrom +flash bank $_FLASHNAME mini51 0x00100000 0x1000 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_conf +flash bank $_FLASHNAME mini51 0x00300000 0x0100 0 0 $_TARGETNAME + +# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter_khz 1000 + +adapter_nsrst_delay 100 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} |