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authorPaul Fertser <fercerpav@gmail.com>2015-01-10 13:19:26 +0300
committerSpencer Oliver <spen@spen-soft.co.uk>2015-01-26 20:54:51 +0000
commita1bbf4b75bc68aeed3c72e37b302bb36757401c2 (patch)
tree6a60ed0faa53c7aead5f62c4f6fe162b48d14df6 /tcl/target
parent7dd50909e32296fc4ceff64d8443f5b9fa75bbca (diff)
cfg: add srst_nogate to the supported targets, remove from board configs
It depends on the particular target whether it can work with SRST asserted or not, so this belongs to the target config rather than the board config. Also, this allows for simple openocd -f myboard.cfg -c "reset_config connect_assert_srst" command to be used whenever a user feels a need to connect to an unresponsive target. Change-Id: I3d8da9ae47088fc0c75a20bfdd20074be1014de0 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2459 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl/target')
-rw-r--r--tcl/target/k40.cfg3
-rw-r--r--tcl/target/k60.cfg3
-rw-r--r--tcl/target/kl25.cfg2
-rw-r--r--tcl/target/stm32f0x.cfg2
-rw-r--r--tcl/target/stm32f1x.cfg2
-rw-r--r--tcl/target/stm32f2x.cfg2
-rw-r--r--tcl/target/stm32f3x.cfg2
-rw-r--r--tcl/target/stm32f4x.cfg2
-rw-r--r--tcl/target/stm32l0.cfg2
-rw-r--r--tcl/target/stm32l1.cfg2
-rw-r--r--tcl/target/stm32w108xx.cfg2
11 files changed, 20 insertions, 4 deletions
diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg
index a139dcdb..b0f69940 100644
--- a/tcl/target/k40.cfg
+++ b/tcl/target/k40.cfg
@@ -31,8 +31,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
-$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
-$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
+reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/k60.cfg b/tcl/target/k60.cfg
index a368e0b2..0e7adc4a 100644
--- a/tcl/target/k60.cfg
+++ b/tcl/target/k60.cfg
@@ -31,8 +31,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
-$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
-$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
+reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/kl25.cfg b/tcl/target/kl25.cfg
index 7b14ecc8..b75e0a56 100644
--- a/tcl/target/kl25.cfg
+++ b/tcl/target/kl25.cfg
@@ -55,6 +55,8 @@ flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
# specifies up to 1MHz for VLPR mode.
adapter_khz 1000
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index 30ea7171..ff6d7f14 100644
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -46,6 +46,8 @@ adapter_khz 1000
adapter_nsrst_delay 100
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 46d70b1e..6a62992d 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -86,6 +86,8 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 62e35a4c..0ac73a51 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -70,6 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 4ad4bd57..9547d843 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -70,6 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index faa6a7e5..fd5cab6a 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -82,6 +82,8 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index 45b3c364..fd8f951b 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -46,6 +46,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index ccbec09d..8591830c 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -75,6 +75,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg
index 864917f4..1a191354 100644
--- a/tcl/target/stm32w108xx.cfg
+++ b/tcl/target/stm32w108xx.cfg
@@ -63,6 +63,8 @@ set _FLASHNAME $_CHIPNAME.flash
# 64k (0x10000) of flash
flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME
+reset_config srst_nogate
+
if {![using_hla]} {
cortex_m reset_config sysresetreq
}