flash: add stm32f3x support

add support for the new stm32f3x family from stmicro:
http://www.st.com/stm32f3

Change-Id: Icd1db95bb2767d9c0ecef24deefa92b4fdaa4f14
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/735
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

2 files changed, 83 insertions, 0 deletions

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
new file mode 100644
index 00000000..1f051434
--- /dev/null
+++ b/tcl/target/stm32f3x.cfg
@@ -0,0 +1,63 @@
+# script for stm32f3x family
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f3x
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0316
+  # Section 29.6.3 - corresponds to Cortex-M4 r0p1
+   set _CPUTAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0316
+  # Section 29.6.2
+  set _BSTAPID 0x06432041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq
diff --git a/tcl/target/stm32f3x_stlink.cfg b/tcl/target/stm32f3x_stlink.cfg
new file mode 100644
index 00000000..bc86ed94
--- /dev/null
+++ b/tcl/target/stm32f3x_stlink.cfg
@@ -0,0 +1,20 @@
+#
+# STM32f3x stlink pseudo target
+#
+
+if { [info exists CHIPNAME] == 0 } {
+   set CHIPNAME stm32f3x
+}
+
+if { [info exists CPUTAPID] == 0 } {
+   set CPUTAPID 0x1ba01477
+}
+
+if { [info exists WORKAREASIZE] == 0 } {
+   set WORKAREASIZE 0x4000
+}
+
+source [find target/stm32_stlink.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME