diff options
author | Leonard Crestez <leonard.crestez@nxp.com> | 2019-04-04 22:25:49 +0300 |
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committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-04-24 14:11:22 +0100 |
commit | b13055069c12fe0f8d60777b37f0df39d883e359 (patch) | |
tree | f2b22ef651f585a84642f3efbc76fba5efd6437b /tcl/target | |
parent | 537bbefcbd693d3c544c7d12e015d615193d0c82 (diff) |
target/imx6sx: Initial support
Unlike the rest of imx6 a Cortex-M4 was added with a second CoreSight
DAP so a separate script is required.
Tested on imx6sx-sdb running linux
Change-Id: I1561910b233015f42508f341175822c0827655ec
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-on: http://openocd.zylin.com/5041
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'tcl/target')
-rw-r--r-- | tcl/target/imx6sx.cfg | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/tcl/target/imx6sx.cfg b/tcl/target/imx6sx.cfg new file mode 100644 index 00000000..d3fae8a9 --- /dev/null +++ b/tcl/target/imx6sx.cfg @@ -0,0 +1,50 @@ +# +# Freescale i.MX6SoloX +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx6sx +} + +# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9 +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID +dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4 + +jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID +dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9 + +# SDMA / no IDCODE +jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f + +# System JTAG Controller +if { [info exists SJC_TAPID] } { + set _SJC_TAPID $SJC_TAPID +} else { + set _SJC_TAPID 0x0891c01d +} +jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ + -expected-id $_SJC_TAPID -ignore-version + +# Cortex-A9 (boot core) +target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \ + -coreid 0 -dbgbase 0x82150000 + +# Cortex-M4 (default off) +target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \ + -ap-num 0 -defer-examine + +# AHB mem-ap target +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0 + +# Default target is Cortex-A9 +targets $_CHIPNAME.cpu_a9 |