diff options
| author | Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> | 2016-05-18 10:59:29 +0200 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2016-05-20 21:13:52 +0100 |
| commit | 44a6362b20fdb24b002f36c7b3b5529fe91db8ac (patch) | |
| tree | 5b60d6091019624e0f17a7b2a5bb437e7677d4b9 /tcl/target | |
| parent | 89bf96ffe6ac66c80407af8383b9d5adc0dc35f4 (diff) | |
stm32l4x.cfg: Fix RCC_CR address.
Change-Id: I7a63d24a495e28bc01b5e6603f15b88e075878b8
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3489
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/stm32l4x.cfg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg index 8b827adc..65169942 100644 --- a/tcl/target/stm32l4x.cfg +++ b/tcl/target/stm32l4x.cfg @@ -84,7 +84,7 @@ $_TARGETNAME configure -event reset-init { # Configure system to use MSI 24 MHz clock, compliant with VOS default (2). # 3 WS compliant with VOS=2 and 24 MHz. mww 0x40022000 0x00000102 ;# FLASH_ACR = PRFTBE | 3(Latency) - mww 0x4002100C 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10 + mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10 # Boost JTAG frequency adapter_khz 4000 } |